[coreboot-gerrit] Change in coreboot[master]: src/arch: Fix checkpatch warning: no spaces at the start of a line
Martin Roth (Code Review)
gerrit at coreboot.org
Mon Jul 24 04:14:56 CEST 2017
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20728
Change subject: src/arch: Fix checkpatch warning: no spaces at the start of a line
......................................................................
src/arch: Fix checkpatch warning: no spaces at the start of a line
Change-Id: Id9846ceb714dceaea12ea33ce2aa2b8e5bb6f4df
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/arch/arm/cpu.c
M src/arch/riscv/include/arch/encoding.h
M src/arch/riscv/include/atomic.h
M src/arch/riscv/include/mcall.h
M src/arch/riscv/include/vm.h
5 files changed, 46 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20728/1
diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c
index e138a6f..fae1a37 100644
--- a/src/arch/arm/cpu.c
+++ b/src/arch/arm/cpu.c
@@ -35,10 +35,10 @@
struct cpu_info *cpu_info(void)
{
#error "This is BROKEN! ARM stacks are currently not guaranteed to be " \
- "STACK_SIZE-aligned in any way. If you ever plan to revive this " \
- "feature, make sure you add the proper assertions " \
- "(and maybe consider revising the whole thing to work closer to what " \
- "arm64 is doing now)."
+ "STACK_SIZE-aligned in any way. If you ever plan to revive this " \
+ "feature, make sure you add the proper assertions " \
+ "(and maybe consider revising the whole thing to work closer to what " \
+ "arm64 is doing now)."
uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0),
CONFIG_STACK_SIZE);
addr -= sizeof(struct cpu_info);
diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h
index d40446b..5142a78 100644
--- a/src/arch/riscv/include/arch/encoding.h
+++ b/src/arch/riscv/include/arch/encoding.h
@@ -198,35 +198,35 @@
#ifdef __GNUC__
#define read_csr(reg) ({ unsigned long __tmp; \
- asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
- __tmp; })
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
#define write_csr(reg, val) ({ \
- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
- asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
- else \
- asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+ else \
+ asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
#define swap_csr(reg, val) ({ unsigned long __tmp; \
- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
- else \
- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
- __tmp; })
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+ else \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+ __tmp; })
#define set_csr(reg, bit) ({ unsigned long __tmp; \
- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
- else \
- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
- __tmp; })
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
- else \
- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
- __tmp; })
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
#define rdtime() read_csr(time)
#define rdcycle() read_csr(cycle)
diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h
index 639b54a..bc739fb 100644
--- a/src/arch/riscv/include/atomic.h
+++ b/src/arch/riscv/include/atomic.h
@@ -45,23 +45,23 @@
# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)
#else
# define atomic_add(ptr, inc) ({ \
- long flags = disable_irqsave(); \
- typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
- *(volatile typeof(ptr))(ptr) = res + (inc); \
- enable_irqrestore(flags); \
- res; })
+ long flags = disable_irqsave(); \
+ typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
+ *(volatile typeof(ptr))(ptr) = res + (inc); \
+ enable_irqrestore(flags); \
+ res; })
# define atomic_swap(ptr, swp) ({ \
- long flags = disable_irqsave(); \
- typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \
- *(volatile typeof(ptr))(ptr) = (swp); \
- enable_irqrestore(flags); \
- res; })
+ long flags = disable_irqsave(); \
+ typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \
+ *(volatile typeof(ptr))(ptr) = (swp); \
+ enable_irqrestore(flags); \
+ res; })
# define atomic_cas(ptr, cmp, swp) ({ \
- long flags = disable_irqsave(); \
- typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
- if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \
- enable_irqrestore(flags); \
- res; })
+ long flags = disable_irqsave(); \
+ typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
+ if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \
+ enable_irqrestore(flags); \
+ res; })
#endif
#endif
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index cdd9bd3..fe9611c 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -70,9 +70,9 @@
} hls_t;
#define MACHINE_STACK_TOP() ({ \
- /* coverity[uninit_use] : FALSE */ \
- register uintptr_t sp asm ("sp"); \
- (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })
+ /* coverity[uninit_use] : FALSE */ \
+ register uintptr_t sp asm ("sp"); \
+ (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })
// hart-local storage, at top of stack
#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE))
diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h
index c3de47a..a65aba9 100644
--- a/src/arch/riscv/include/vm.h
+++ b/src/arch/riscv/include/vm.h
@@ -41,9 +41,9 @@
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#define supervisor_paddr_valid(start, length) \
- ((uintptr_t)(start) >= current.first_user_vaddr + current.bias \
- && (uintptr_t)(start) + (length) < mem_size \
- && (uintptr_t)(start) + (length) >= (uintptr_t)(start))
+ ((uintptr_t)(start) >= current.first_user_vaddr + current.bias \
+ && (uintptr_t)(start) + (length) < mem_size \
+ && (uintptr_t)(start) + (length) >= (uintptr_t)(start))
typedef uintptr_t pte_t;
extern pte_t* root_page_table;
--
To view, visit https://review.coreboot.org/20728
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id9846ceb714dceaea12ea33ce2aa2b8e5bb6f4df
Gerrit-Change-Number: 20728
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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