<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20728">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/arch: Fix checkpatch warning: no spaces at the start of a line<br><br>Change-Id: Id9846ceb714dceaea12ea33ce2aa2b8e5bb6f4df<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/arch/arm/cpu.c<br>M src/arch/riscv/include/arch/encoding.h<br>M src/arch/riscv/include/atomic.h<br>M src/arch/riscv/include/mcall.h<br>M src/arch/riscv/include/vm.h<br>5 files changed, 46 insertions(+), 46 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20728/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c<br>index e138a6f..fae1a37 100644<br>--- a/src/arch/arm/cpu.c<br>+++ b/src/arch/arm/cpu.c<br>@@ -35,10 +35,10 @@<br> struct cpu_info *cpu_info(void)<br> {<br> #error "This is BROKEN! ARM stacks are currently not guaranteed to be " \<br>- "STACK_SIZE-aligned in any way. If you ever plan to revive this " \<br>- "feature, make sure you add the proper assertions " \<br>- "(and maybe consider revising the whole thing to work closer to what " \<br>- "arm64 is doing now)."<br>+ "STACK_SIZE-aligned in any way. If you ever plan to revive this " \<br>+ "feature, make sure you add the proper assertions " \<br>+ "(and maybe consider revising the whole thing to work closer to what " \<br>+ "arm64 is doing now)."<br> uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0),<br> CONFIG_STACK_SIZE);<br> addr -= sizeof(struct cpu_info);<br>diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h<br>index d40446b..5142a78 100644<br>--- a/src/arch/riscv/include/arch/encoding.h<br>+++ b/src/arch/riscv/include/arch/encoding.h<br>@@ -198,35 +198,35 @@<br> #ifdef __GNUC__<br> <br> #define read_csr(reg) ({ unsigned long __tmp; \<br>- asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \<br>- __tmp; })<br>+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \<br>+ __tmp; })<br> <br> #define write_csr(reg, val) ({ \<br>- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \<br>- asm volatile ("csrw " #reg ", %0" :: "i"(val)); \<br>- else \<br>- asm volatile ("csrw " #reg ", %0" :: "r"(val)); })<br>+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \<br>+ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \<br>+ else \<br>+ asm volatile ("csrw " #reg ", %0" :: "r"(val)); })<br> <br> #define swap_csr(reg, val) ({ unsigned long __tmp; \<br>- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \<br>- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \<br>- else \<br>- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \<br>- __tmp; })<br>+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \<br>+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \<br>+ else \<br>+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \<br>+ __tmp; })<br> <br> #define set_csr(reg, bit) ({ unsigned long __tmp; \<br>- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \<br>- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \<br>- else \<br>- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \<br>- __tmp; })<br>+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \<br>+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \<br>+ else \<br>+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \<br>+ __tmp; })<br> <br> #define clear_csr(reg, bit) ({ unsigned long __tmp; \<br>- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \<br>- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \<br>- else \<br>- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \<br>- __tmp; })<br>+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \<br>+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \<br>+ else \<br>+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \<br>+ __tmp; })<br> <br> #define rdtime() read_csr(time)<br> #define rdcycle() read_csr(cycle)<br>diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h<br>index 639b54a..bc739fb 100644<br>--- a/src/arch/riscv/include/atomic.h<br>+++ b/src/arch/riscv/include/atomic.h<br>@@ -45,23 +45,23 @@<br> # define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)<br> #else<br> # define atomic_add(ptr, inc) ({ \<br>- long flags = disable_irqsave(); \<br>- typeof(ptr) res = *(volatile typeof(ptr))(ptr); \<br>- *(volatile typeof(ptr))(ptr) = res + (inc); \<br>- enable_irqrestore(flags); \<br>- res; })<br>+ long flags = disable_irqsave(); \<br>+ typeof(ptr) res = *(volatile typeof(ptr))(ptr); \<br>+ *(volatile typeof(ptr))(ptr) = res + (inc); \<br>+ enable_irqrestore(flags); \<br>+ res; })<br> # define atomic_swap(ptr, swp) ({ \<br>- long flags = disable_irqsave(); \<br>- typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \<br>- *(volatile typeof(ptr))(ptr) = (swp); \<br>- enable_irqrestore(flags); \<br>- res; })<br>+ long flags = disable_irqsave(); \<br>+ typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \<br>+ *(volatile typeof(ptr))(ptr) = (swp); \<br>+ enable_irqrestore(flags); \<br>+ res; })<br> # define atomic_cas(ptr, cmp, swp) ({ \<br>- long flags = disable_irqsave(); \<br>- typeof(ptr) res = *(volatile typeof(ptr))(ptr); \<br>- if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \<br>- enable_irqrestore(flags); \<br>- res; })<br>+ long flags = disable_irqsave(); \<br>+ typeof(ptr) res = *(volatile typeof(ptr))(ptr); \<br>+ if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \<br>+ enable_irqrestore(flags); \<br>+ res; })<br> #endif<br> <br> #endif<br>diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h<br>index cdd9bd3..fe9611c 100644<br>--- a/src/arch/riscv/include/mcall.h<br>+++ b/src/arch/riscv/include/mcall.h<br>@@ -70,9 +70,9 @@<br> } hls_t;<br> <br> #define MACHINE_STACK_TOP() ({ \<br>- /* coverity[uninit_use] : FALSE */ \<br>- register uintptr_t sp asm ("sp"); \<br>- (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })<br>+ /* coverity[uninit_use] : FALSE */ \<br>+ register uintptr_t sp asm ("sp"); \<br>+ (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })<br> <br> // hart-local storage, at top of stack<br> #define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE))<br>diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h<br>index c3de47a..a65aba9 100644<br>--- a/src/arch/riscv/include/vm.h<br>+++ b/src/arch/riscv/include/vm.h<br>@@ -41,9 +41,9 @@<br> #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))<br> <br> #define supervisor_paddr_valid(start, length) \<br>- ((uintptr_t)(start) >= current.first_user_vaddr + current.bias \<br>- && (uintptr_t)(start) + (length) < mem_size \<br>- && (uintptr_t)(start) + (length) >= (uintptr_t)(start))<br>+ ((uintptr_t)(start) >= current.first_user_vaddr + current.bias \<br>+ && (uintptr_t)(start) + (length) < mem_size \<br>+ && (uintptr_t)(start) + (length) >= (uintptr_t)(start))<br> <br> typedef uintptr_t pte_t;<br> extern pte_t* root_page_table;<br></pre><p>To view, visit <a href="https://review.coreboot.org/20728">change 20728</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20728"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id9846ceb714dceaea12ea33ce2aa2b8e5bb6f4df </div>
<div style="display:none"> Gerrit-Change-Number: 20728 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>