[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Modify fast_spi_lock_bar function

[Barnali Sarkar (Code Review)]

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20643


Change subject: soc/intel/common/block: Modify fast_spi_lock_bar function
......................................................................

soc/intel/common/block: Modify fast_spi_lock_bar function

Use 16bit write to avoid touching the upper two bytes that may cause
write cycle to fail in case a prior transaction has not completed.

This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the
SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN,
writing both in the same cycle is guaranteed to work by design.

Avoide read->modify->write operation not to clear the RW1C bits
unintentionally.

Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
2 files changed, 10 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20643/1

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 1ef929c..9f3b190 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -119,15 +119,20 @@
 
 /*
  * Lock FAST_SPIBAR.
+ * Use 16bit write to avoid touching two upper bytes what may cause the write
+ * cycle to fail in case a prior transaction has not completed.
+ * While WRSDIS is lockable with FLOCKDN, writing both in the same
+ * cycle is guaranteed to work by design.
+ *
+ * Avoid read->modify->write not to clear RW1C bits unintentionally.
  */
 void fast_spi_lock_bar(void)
 {
 	void *spibar = fast_spi_get_bar();
-	uint32_t hsfs;
+	uint16_t hsfs;
 
-	hsfs = read32(spibar + SPIBAR_HSFSTS_CTL);
-	hsfs |= SPIBAR_HSFSTS_FLOCKDN;
-	write32(spibar + SPIBAR_HSFSTS_CTL, hsfs);
+	hsfs = (uint16_t) (SPIBAR_HSFSTS_FLOCKDN |SPIBAR_HSFSTS_WRSDIS);
+	write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);
 }
 
 /*
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
index 1262e6a..516b42d 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -70,6 +70,7 @@
 #define SPIBAR_HSFSTS_FLOCKDN		(1 << 15)
 #define SPIBAR_HSFSTS_FDV		(1 << 14)
 #define SPIBAR_HSFSTS_FDOPSS		(1 << 13)
+#define SPIBAR_HSFSTS_WRSDIS		(1 << 11)
 #define SPIBAR_HSFSTS_SAF_CE		(1 << 8)
 #define SPIBAR_HSFSTS_SAF_ACTIVE	(1 << 7)
 #define SPIBAR_HSFSTS_SAF_LE		(1 << 6)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b
Gerrit-Change-Number: 20643
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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