<p>Barnali Sarkar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20643">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Modify fast_spi_lock_bar function<br><br>Use 16bit write to avoid touching the upper two bytes that may cause<br>write cycle to fail in case a prior transaction has not completed.<br><br>This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the<br>SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN,<br>writing both in the same cycle is guaranteed to work by design.<br><br>Avoide read->modify->write operation not to clear the RW1C bits<br>unintentionally.<br><br>Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b<br>Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com><br>---<br>M src/soc/intel/common/block/fast_spi/fast_spi.c<br>M src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>2 files changed, 10 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20643/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c<br>index 1ef929c..9f3b190 100644<br>--- a/src/soc/intel/common/block/fast_spi/fast_spi.c<br>+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c<br>@@ -119,15 +119,20 @@<br> <br> /*<br>  * Lock FAST_SPIBAR.<br>+ * Use 16bit write to avoid touching two upper bytes what may cause the write<br>+ * cycle to fail in case a prior transaction has not completed.<br>+ * While WRSDIS is lockable with FLOCKDN, writing both in the same<br>+ * cycle is guaranteed to work by design.<br>+ *<br>+ * Avoid read->modify->write not to clear RW1C bits unintentionally.<br>  */<br> void fast_spi_lock_bar(void)<br> {<br>     void *spibar = fast_spi_get_bar();<br>-   uint32_t hsfs;<br>+       uint16_t hsfs;<br> <br>-    hsfs = read32(spibar + SPIBAR_HSFSTS_CTL);<br>-   hsfs |= SPIBAR_HSFSTS_FLOCKDN;<br>-       write32(spibar + SPIBAR_HSFSTS_CTL, hsfs);<br>+   hsfs = (uint16_t) (SPIBAR_HSFSTS_FLOCKDN |SPIBAR_HSFSTS_WRSDIS);<br>+     write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);<br> }<br> <br> /*<br>diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>index 1262e6a..516b42d 100644<br>--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>@@ -70,6 +70,7 @@<br> #define SPIBAR_HSFSTS_FLOCKDN              (1 << 15)<br> #define SPIBAR_HSFSTS_FDV             (1 << 14)<br> #define SPIBAR_HSFSTS_FDOPSS          (1 << 13)<br>+#define SPIBAR_HSFSTS_WRSDIS          (1 << 11)<br> #define SPIBAR_HSFSTS_SAF_CE          (1 << 8)<br> #define SPIBAR_HSFSTS_SAF_ACTIVE       (1 << 7)<br> #define SPIBAR_HSFSTS_SAF_LE           (1 << 6)<br></pre><p>To view, visit <a href="https://review.coreboot.org/20643">change 20643</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20643"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b </div>
<div style="display:none"> Gerrit-Change-Number: 20643 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Barnali Sarkar <barnali.sarkar@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>