[coreboot-gerrit] Change in coreboot[master]: intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0

[Werner Zeh (Code Review)]

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/20680


Change subject: intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0
......................................................................

intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0

Current implementation of itss_irq_init() uses 8 bit write access to
IRQ routing registers which is not supported on Apollo Lake.
This commit extends the function to write the routing register
32 bit wide if the Kconfig switch PCR_COMMON_IOSF_1_0 is selected.

Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094
Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
M src/soc/intel/common/block/itss/itss.c
1 file changed, 18 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/20680/1

diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c
index a217675..d15073d 100644
--- a/src/soc/intel/common/block/itss/itss.c
+++ b/src/soc/intel/common/block/itss/itss.c
@@ -24,6 +24,7 @@
 void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG])
 {
 	uint8_t index = 0;
+	uint32_t val32 = 0x80808080; /* Disable interrupts per default. */
 
 	for (index = 0; index < MAX_PXRC_CONFIG; index++) {
 		uint8_t val = pch_interrupt_routing[index];
@@ -34,7 +35,23 @@
 		if (irq <= 2)
 			continue;
 
-		pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index, val);
+		if (IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)) {
+			uint8_t byte = (index % sizeof(uint32_t));
+			/* If an interrupt is supported clear disable bit */
+			val32 &= ~(0xff << (8 * byte));
+			/* and set the matching bits to given IRQ value. */
+			val32 |= (val << (8 * byte));
+			/* Write to ITSS register 4 byte at once (0...3). */
+			if (byte == 3) {
+				pcr_write32(PID_ITSS,
+					ALIGN_DOWN(PCR_ITSS_PIRQA_ROUT + index,
+						   sizeof(uint32_t)),
+					val32);
+				val32 = 0x80808080;
+			}
+		} else {
+			pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index, val);
+		}
 	}
 }
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094
Gerrit-Change-Number: 20680
Gerrit-PatchSet: 1
Gerrit-Owner: Werner Zeh <werner.zeh at siemens.com>
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