<p>Werner Zeh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20680">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0<br><br>Current implementation of itss_irq_init() uses 8 bit write access to<br>IRQ routing registers which is not supported on Apollo Lake.<br>This commit extends the function to write the routing register<br>32 bit wide if the Kconfig switch PCR_COMMON_IOSF_1_0 is selected.<br><br>Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094<br>Signed-off-by: Werner Zeh <werner.zeh@siemens.com><br>---<br>M src/soc/intel/common/block/itss/itss.c<br>1 file changed, 18 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/20680/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c<br>index a217675..d15073d 100644<br>--- a/src/soc/intel/common/block/itss/itss.c<br>+++ b/src/soc/intel/common/block/itss/itss.c<br>@@ -24,6 +24,7 @@<br> void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG])<br> {<br>   uint8_t index = 0;<br>+   uint32_t val32 = 0x80808080; /* Disable interrupts per default. */<br> <br>         for (index = 0; index < MAX_PXRC_CONFIG; index++) {<br>                uint8_t val = pch_interrupt_routing[index];<br>@@ -34,7 +35,23 @@<br>               if (irq <= 2)<br>                      continue;<br> <br>-         pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index, val);<br>+              if (IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)) {<br>+                        uint8_t byte = (index % sizeof(uint32_t));<br>+                   /* If an interrupt is supported clear disable bit */<br>+                 val32 &= ~(0xff << (8 * byte));<br>+                    /* and set the matching bits to given IRQ value. */<br>+                  val32 |= (val << (8 * byte));<br>+                  /* Write to ITSS register 4 byte at once (0...3). */<br>+                 if (byte == 3) {<br>+                             pcr_write32(PID_ITSS,<br>+                                        ALIGN_DOWN(PCR_ITSS_PIRQA_ROUT + index,<br>+                                                 sizeof(uint32_t)),<br>+                                        val32);<br>+                              val32 = 0x80808080;<br>+                  }<br>+            } else {<br>+                     pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index, val);<br>+              }<br>     }<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/20680">change 20680</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20680"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094 </div>
<div style="display:none"> Gerrit-Change-Number: 20680 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Werner Zeh <werner.zeh@siemens.com> </div>