[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Perform LPC offset read after lockdown operation

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20678


Change subject: soc/intel/skylake: Perform LPC offset read after lockdown operation
......................................................................

soc/intel/skylake: Perform LPC offset read after lockdown operation

This patch is to provide an additional read LPC pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.

Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/finalize.c
1 file changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/20678/1

diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 171d92e..34f26eb 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -185,6 +185,9 @@
 				  pci_read_config8(PCH_DEV_LPC,
 						   BIOS_CNTL) | LPC_BC_LE);
 
+		/* Ensure an additional read back after performing lock down */
+		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
+
 		fast_spi_set_lock_enable();
 	}
 
@@ -194,6 +197,9 @@
 				  pci_read_config8(PCH_DEV_LPC,
 						   BIOS_CNTL) | LPC_BC_EISS);
 
+		/* Ensure an additional read back after performing lock down */
+		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
+
 		fast_spi_set_eiss();
 	}
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874
Gerrit-Change-Number: 20678
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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