[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Update memory HOB info save function

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/20674


Change subject: soc/intel/apollolake: Update memory HOB info save function
......................................................................

soc/intel/apollolake: Update memory HOB info save function

SMBIOS memory HOB produced by glk FSP has new structure members,
update memory HOB save routine to reflect new changes.

Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
M src/soc/intel/apollolake/meminit.c
1 file changed, 36 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/20674/1

diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 0a69674..a5c2fce 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -268,6 +268,9 @@
 	struct memory_info *mem_info;
 	const CHANNEL_INFO *channel_info;
 	const FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+	int node;
+#endif
 
 	if (mem_sku >= lp4cfg->num_skus) {
 		printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n",
@@ -291,6 +294,38 @@
 	/* Describe the first N DIMMs in the system */
 	index = 0;
 	dimm_max = ARRAY_SIZE(mem_info->dimm);
+
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+	for (node = 0; node < MAX_NODE_NUM; node++) {
+		for (channel = 0; channel < memory_info_hob->Controller[node].ChannelCount;
+					channel++) {
+			if (index >= dimm_max)
+				break;
+			channel_info = &memory_info_hob->Controller[node].ChannelInfo[channel];
+			for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
+				if (index >= dimm_max)
+					break;
+				src_dimm = &channel_info->DimmInfo[dimm];
+				dest_dimm = &mem_info->dimm[index];
+
+				if (!src_dimm->DimmCapacity)
+					continue;
+
+				/* Populate the DIMM information */
+				dimm_info_fill(dest_dimm,
+					src_dimm->DimmCapacity,
+					memory_info_hob->MemoryType,
+					memory_info_hob->ConfiguredMemoryClockSpeed,
+					channel_info->ChannelId,
+					src_dimm->DimmId,
+					lp4cfg->skus[mem_sku].part_num,
+					strlen(lp4cfg->skus[mem_sku].part_num),
+					memory_info_hob->DataWidth);
+				index++;
+			}
+		}
+	}
+#else
 	for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
 		if (index >= dimm_max)
 			break;
@@ -317,6 +352,7 @@
 			index++;
 		}
 	}
+#endif
 	mem_info->dimm_cnt = index;
 	printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6
Gerrit-Change-Number: 20674
Gerrit-PatchSet: 1
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
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