[coreboot-gerrit] Change in coreboot[master]: [WIP] utils/inteltool: Add support for Haswell-E/Wellsburg dumping
Omar Pakker (Code Review)
gerrit at coreboot.org
Thu Jul 20 21:36:06 CEST 2017
Omar Pakker has uploaded this change for review. ( https://review.coreboot.org/20669
Change subject: [WIP] utils/inteltool: Add support for Haswell-E/Wellsburg dumping
......................................................................
[WIP] utils/inteltool: Add support for Haswell-E/Wellsburg dumping
This adds support for dumping of Haswell-E and Wellsburg
to the inteltool. MCHBAR, EPBAR, PCIEXBAR and AMBs missing.
Based on these datasheets:
Intel Core i7 Processor Family for LGA2011-v3 vol. 1 & 2, August 2014
Intel C610 Series and Intel X99 Chipset PCH, October 2015
Signed-off-by: Omar Pakker <coreboot at opakker.nl>
Change-Id: I73d289b9fc2064ba53dd0395680523be72adf490
---
M util/inteltool/gpio.c
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcie.c
M util/inteltool/powermgt.c
M util/inteltool/rootcmplx.c
M util/inteltool/spi.c
7 files changed, 89 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/20669/1
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 5fd160b..0ad4463 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -460,6 +460,30 @@
{ 0x80 + 0x38, 4, "SUS_WAKE_EN_43_32_" }
};
+/* Wellsburg (X99/C610) */
+static const gpio_default_t wellsburg_defaults[] = {
+ { 0x00, 0x9F7FA1FF },
+ { 0x04, 0xC8EB6EFF },
+ { 0x0c, 0x22FE1100 },
+ { 0x18, 0x00040000 },
+ { 0x1c, 0x00000000 },
+ { 0x20, 0x00080000 },
+ { 0x24, 0x00000000 },
+ { 0x28, 0x0000 },
+ { 0x2a, 0x0000 },
+ { 0x2c, 0x00000000 },
+ { 0x30, 0x2383F0FF },
+ { 0x34, 0x1F57FFF4 },
+ { 0x38, 0xA4AA0007 },
+ { 0x40, 0x00000330 },
+ { 0x44, 0x00000FF0 },
+ { 0x48, 0x000000C0 },
+ { 0x4c, 0x00000000 },
+ { 0x60, 0x01000000 },
+ { 0x64, 0x00000000 },
+ { 0x68, 0x00000000 },
+};
+
/* Description of GPIO 'bank' ex. {ncore, score. ssus} */
struct gpio_bank {
const uint32_t gpio_count;
@@ -940,6 +964,13 @@
gpio_defaults = pp_pch_mobile_defaults;
defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults);
break;
+ case PCI_DEVICE_ID_INTEL_WELLSBURG:
+ gpiobase = pci_read_word(sb, 0x48) & 0xff80;
+ gpio_registers = pch_gpio_registers;
+ size = ARRAY_SIZE(pch_gpio_registers);
+ gpio_defaults = wellsburg_defaults;
+ defaults_size = ARRAY_SIZE(wellsburg_defaults);
+ break;
case PCI_DEVICE_ID_INTEL_ICH10:
case PCI_DEVICE_ID_INTEL_ICH10R:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
@@ -999,7 +1030,6 @@
gpio_registers = ich0_gpio_registers;
size = ARRAY_SIZE(ich0_gpio_registers);
break;
-
case PCI_DEVICE_ID_INTEL_I63XX:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = i631x_gpio_registers;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index ccb8fac..8c2e4b6 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -103,6 +103,8 @@
"3rd generation (Ivy Bridge family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D,
"4th generation (Haswell family) Core Processor (Desktop)" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E,
+ "4th generation (Haswell family) Core Processor (Extreme)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M,
"4th generation (Haswell family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3,
@@ -112,7 +114,8 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U,
"5th generation (Broadwell family) Core Processor ULT" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, "6th generation (Skylake-S/H family) Core Processor (Workstation)" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST,
+ "6th generation (Skylake-S/H family) Core Processor (Workstation)" },
/* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" },
@@ -201,6 +204,8 @@
{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM236, "CM236" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG,
+ "Wellsburg (X99/C610)" },
};
#ifndef __DARWIN__
@@ -270,7 +275,8 @@
int main(int argc, char *argv[])
{
struct pci_access *pacc;
- struct pci_dev *sb = NULL, *nb, *gfx = NULL, *ahci = NULL, *dev;
+ struct pci_dev *sb = NULL, *nb, *gfx = NULL, *dev;
+ struct pci_dev *ahci = NULL, *ahci2 = NULL;
const char *dump_spd_file = NULL;
int i, opt, option_index = 0;
unsigned int id;
@@ -449,13 +455,13 @@
}
gfx = pci_get_dev(pacc, 0, 0, 0x02, 0);
-
if (gfx) {
pci_fill_info(gfx, PCI_FILL_IDENT | PCI_FILL_BASES |
PCI_FILL_CLASS);
- if (gfx->vendor_id != PCI_VENDOR_ID_INTEL)
- gfx = 0;
+ if (gfx->vendor_id != PCI_VENDOR_ID_INTEL ||
+ gfx->device_class != PCI_CLASS_DISPLAY_VGA)
+ gfx = NULL;
}
if (sb->device_id == PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC) {
@@ -464,18 +470,25 @@
ahci = pci_get_dev(pacc, 0, 0, 0x1f, 2);
if (ahci) {
pci_fill_info(ahci, PCI_FILL_CLASS);
- if (ahci->device_class != PCI_CLASS_STORAGE_SATA)
+ if (ahci->device_class != PCI_CLASS_STORAGE_SATA &&
+ ahci->device_class != PCI_CLASS_STORAGE_RAID)
ahci = pci_get_dev(pacc, 0, 0, 0x17, 0);
}
}
if (ahci) {
pci_fill_info(ahci, PCI_FILL_IDENT | PCI_FILL_BASES |
- PCI_FILL_CLASS);
-
+ PCI_FILL_CLASS);
if (ahci->vendor_id != PCI_VENDOR_ID_INTEL ||
- ahci->device_class != PCI_CLASS_STORAGE_SATA)
+ (ahci->device_class != PCI_CLASS_STORAGE_SATA &&
+ ahci->device_class != PCI_CLASS_STORAGE_RAID))
ahci = NULL;
+ }
+
+ if (sb->device_id == PCI_DEVICE_ID_INTEL_WELLSBURG) {
+ ahci2 = pci_get_dev(pacc, 0, 0, 0x11, 4);
+ pci_fill_info(ahci2, PCI_FILL_IDENT | PCI_FILL_BASES |
+ PCI_FILL_CLASS);
}
id = cpuid(1);
@@ -573,11 +586,14 @@
if (dump_ahci) {
print_ahci(ahci);
+ print_ahci(ahci2);
}
/* Clean up */
if (ahci)
pci_free_dev(ahci);
+ if (ahci2)
+ pci_free_dev(ahci2);
if (gfx)
pci_free_dev(gfx);
pci_free_dev(nb);
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index e463260..73ebe04 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -140,6 +140,7 @@
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102
#define PCI_DEVICE_ID_INTEL_CM236 0xa150
+#define PCI_DEVICE_ID_INTEL_WELLSBURG 0x8d47
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
@@ -204,6 +205,7 @@
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */
+#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E 0x2f00 /* Haswell (Extreme) */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 67b0e19..e825662 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -171,6 +171,24 @@
/* ... - Reserved */
};
+static const io_register_t haswell_e_dmi_registers[] = {
+ { 0x10, 4, "DMIVC0RCAP" }, //DMI VC0 Resource Capability
+ { 0x14, 4, "DMIVC0RCTL" }, //DMI VC0 Resource Control
+ { 0x1a, 2, "DMIVC0RSTS" }, //DMI VC0 Resource Status
+ { 0x1c, 4, "DMIVC1RCAP" }, //DMI VC1 Resource Capability
+ { 0x20, 4, "DMIVC1RCTL" }, //DMI VC1 Resource Control
+ { 0x26, 2, "DMIVC1RSTS" }, //DMI VC1 Resource Status
+ { 0x28, 4, "DMIVCPRCAP" }, //DMI VCP Resource Capability
+ { 0x2c, 4, "DMIVCPRCTL" }, //DMI VCP Resource Control
+ { 0x32, 2, "DMIVCPRSTS" }, //DMI VCP Resource Status
+ { 0x34, 4, "DMIVCMRCAP" }, //DMI VCM Resource Capability
+ { 0x38, 4, "DMIVCMRCTL" }, //DMI VCM Resource Control
+ { 0x3e, 2, "DMIVCMRSTS" }, //DMI VCM Resource Status
+ { 0x60, 4, "DMIVC1CDTTHROTTLE" }, //DMI VC1 Credit Throttle
+ { 0x64, 4, "DMIVCPCDTTHROTTLE" }, //DMI VCP Credit Throttle
+ { 0x68, 4, "DMIVCMCDTTHROTTLE" }, //DMI VCM Credit Throttle
+};
+
/*
* Egress Port Root Complex MMIO configuration space
*/
@@ -335,7 +353,11 @@
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
break;
-
+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E: //DMIRCBAR
+ dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
+ dmi_registers = haswell_e_dmi_registers;
+ size = ARRAY_SIZE(haswell_e_dmi_registers);
+ break;
default:
printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
return 1;
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index f022904..de03393 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -73,7 +73,8 @@
{ 0x52, 2, "RESERVED" },
{ 0x54, 4, "RESERVED" },
{ 0x58, 4, "RESERVED" },
- { 0x5c, 4, "RESERVED" },
+ { 0x5c, 2, "ALT_GPI_SMI_EN2" },
+ { 0x5e, 2, "ALT_GPI_SMI_STS2" },
/* The TCO registers start here. */
{ 0x60, 2, "TCO_RLD" },
{ 0x62, 1, "TCO_DAT_IN" },
@@ -730,6 +731,7 @@
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
+ case PCI_DEVICE_ID_INTEL_WELLSBURG:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = pch_pm_registers;
size = ARRAY_SIZE(pch_pm_registers);
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index 2ad3410..629df1c 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -97,6 +97,7 @@
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
+ case PCI_DEVICE_ID_INTEL_WELLSBURG:
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
break;
case PCI_DEVICE_ID_INTEL_ICH:
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index cda8667..0300f2a 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -48,8 +48,8 @@
{ 0x7c, 4, "FPR0 Flash Protected Range 2" },
{ 0x80, 4, "FPR0 Flash Protected Range 3" },
{ 0x84, 4, "FPR0 Flash Protected Range 4" },
- { 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
- { 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
+ { 0x90, 1, "SSFS - Software Sequencing Flash Status" },
+ { 0x91, 3, "SSFC - Software Sequencing Flash Control" },
{ 0x94, 2, "PREOP - Prefix opcode Configuration" },
{ 0x96, 2, "OPTYPE - Opcode Type Configuration" },
{ 0x98, 8, "OPMENU - Opcode Menu Configuration" },
@@ -130,6 +130,7 @@
case PCI_DEVICE_ID_INTEL_PM55:
case PCI_DEVICE_ID_INTEL_QM57:
case PCI_DEVICE_ID_INTEL_QS57:
+ case PCI_DEVICE_ID_INTEL_WELLSBURG:
bios_cntl = pci_read_byte(sb, 0xdc);
bios_cntl_register = pch_bios_cntl_registers;
size = ARRAY_SIZE(pch_bios_cntl_registers);
@@ -243,6 +244,7 @@
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
+ case PCI_DEVICE_ID_INTEL_WELLSBURG:
spibaroffset = ICH9_SPIBAR;
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
size = ARRAY_SIZE(spi_bar_registers);
--
To view, visit https://review.coreboot.org/20669
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I73d289b9fc2064ba53dd0395680523be72adf490
Gerrit-Change-Number: 20669
Gerrit-PatchSet: 1
Gerrit-Owner: Omar Pakker
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