<p>Omar Pakker has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20669">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] utils/inteltool: Add support for Haswell-E/Wellsburg dumping<br><br>This adds support for dumping of Haswell-E and Wellsburg<br>to the inteltool. MCHBAR, EPBAR, PCIEXBAR and AMBs missing.<br><br>Based on these datasheets:<br>Intel Core i7 Processor Family for LGA2011-v3 vol. 1 & 2, August 2014<br>Intel C610 Series and Intel X99 Chipset PCH, October 2015<br><br>Signed-off-by: Omar Pakker <coreboot@opakker.nl><br>Change-Id: I73d289b9fc2064ba53dd0395680523be72adf490<br>---<br>M util/inteltool/gpio.c<br>M util/inteltool/inteltool.c<br>M util/inteltool/inteltool.h<br>M util/inteltool/pcie.c<br>M util/inteltool/powermgt.c<br>M util/inteltool/rootcmplx.c<br>M util/inteltool/spi.c<br>7 files changed, 89 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/20669/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c<br>index 5fd160b..0ad4463 100644<br>--- a/util/inteltool/gpio.c<br>+++ b/util/inteltool/gpio.c<br>@@ -460,6 +460,30 @@<br> { 0x80 + 0x38, 4, "SUS_WAKE_EN_43_32_" }<br> };<br> <br>+/* Wellsburg (X99/C610) */<br>+static const gpio_default_t wellsburg_defaults[] = {<br>+ { 0x00, 0x9F7FA1FF },<br>+ { 0x04, 0xC8EB6EFF },<br>+ { 0x0c, 0x22FE1100 },<br>+ { 0x18, 0x00040000 },<br>+ { 0x1c, 0x00000000 },<br>+ { 0x20, 0x00080000 },<br>+ { 0x24, 0x00000000 },<br>+ { 0x28, 0x0000 },<br>+ { 0x2a, 0x0000 },<br>+ { 0x2c, 0x00000000 },<br>+ { 0x30, 0x2383F0FF },<br>+ { 0x34, 0x1F57FFF4 },<br>+ { 0x38, 0xA4AA0007 },<br>+ { 0x40, 0x00000330 },<br>+ { 0x44, 0x00000FF0 },<br>+ { 0x48, 0x000000C0 },<br>+ { 0x4c, 0x00000000 },<br>+ { 0x60, 0x01000000 },<br>+ { 0x64, 0x00000000 },<br>+ { 0x68, 0x00000000 },<br>+};<br>+<br> /* Description of GPIO 'bank' ex. {ncore, score. ssus} */<br> struct gpio_bank {<br> const uint32_t gpio_count;<br>@@ -940,6 +964,13 @@<br> gpio_defaults = pp_pch_mobile_defaults;<br> defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults);<br> break;<br>+ case PCI_DEVICE_ID_INTEL_WELLSBURG:<br>+ gpiobase = pci_read_word(sb, 0x48) & 0xff80;<br>+ gpio_registers = pch_gpio_registers;<br>+ size = ARRAY_SIZE(pch_gpio_registers);<br>+ gpio_defaults = wellsburg_defaults;<br>+ defaults_size = ARRAY_SIZE(wellsburg_defaults);<br>+ break;<br> case PCI_DEVICE_ID_INTEL_ICH10:<br> case PCI_DEVICE_ID_INTEL_ICH10R:<br> gpiobase = pci_read_word(sb, 0x48) & 0xfffc;<br>@@ -999,7 +1030,6 @@<br> gpio_registers = ich0_gpio_registers;<br> size = ARRAY_SIZE(ich0_gpio_registers);<br> break;<br>-<br> case PCI_DEVICE_ID_INTEL_I63XX:<br> gpiobase = pci_read_word(sb, 0x48) & 0xfffc;<br> gpio_registers = i631x_gpio_registers;<br>diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c<br>index ccb8fac..8c2e4b6 100644<br>--- a/util/inteltool/inteltool.c<br>+++ b/util/inteltool/inteltool.c<br>@@ -103,6 +103,8 @@<br> "3rd generation (Ivy Bridge family) Core Processor" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D,<br> "4th generation (Haswell family) Core Processor (Desktop)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E,<br>+ "4th generation (Haswell family) Core Processor (Extreme)" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M,<br> "4th generation (Haswell family) Core Processor (Mobile)" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3,<br>@@ -112,7 +114,8 @@<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U,<br> "5th generation (Broadwell family) Core Processor ULT" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },<br>- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, "6th generation (Skylake-S/H family) Core Processor (Workstation)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST,<br>+ "6th generation (Skylake-S/H family) Core Processor (Workstation)" },<br> /* Southbridges (LPC controllers) */<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" },<br>@@ -201,6 +204,8 @@<br> { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM236, "CM236" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG,<br>+ "Wellsburg (X99/C610)" },<br> };<br> <br> #ifndef __DARWIN__<br>@@ -270,7 +275,8 @@<br> int main(int argc, char *argv[])<br> {<br> struct pci_access *pacc;<br>- struct pci_dev *sb = NULL, *nb, *gfx = NULL, *ahci = NULL, *dev;<br>+ struct pci_dev *sb = NULL, *nb, *gfx = NULL, *dev;<br>+ struct pci_dev *ahci = NULL, *ahci2 = NULL;<br> const char *dump_spd_file = NULL;<br> int i, opt, option_index = 0;<br> unsigned int id;<br>@@ -449,13 +455,13 @@<br> }<br> <br> gfx = pci_get_dev(pacc, 0, 0, 0x02, 0);<br>-<br> if (gfx) {<br> pci_fill_info(gfx, PCI_FILL_IDENT | PCI_FILL_BASES |<br> PCI_FILL_CLASS);<br> <br>- if (gfx->vendor_id != PCI_VENDOR_ID_INTEL)<br>- gfx = 0;<br>+ if (gfx->vendor_id != PCI_VENDOR_ID_INTEL ||<br>+ gfx->device_class != PCI_CLASS_DISPLAY_VGA)<br>+ gfx = NULL;<br> }<br> <br> if (sb->device_id == PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC) {<br>@@ -464,18 +470,25 @@<br> ahci = pci_get_dev(pacc, 0, 0, 0x1f, 2);<br> if (ahci) {<br> pci_fill_info(ahci, PCI_FILL_CLASS);<br>- if (ahci->device_class != PCI_CLASS_STORAGE_SATA)<br>+ if (ahci->device_class != PCI_CLASS_STORAGE_SATA &&<br>+ ahci->device_class != PCI_CLASS_STORAGE_RAID)<br> ahci = pci_get_dev(pacc, 0, 0, 0x17, 0);<br> }<br> }<br> <br> if (ahci) {<br> pci_fill_info(ahci, PCI_FILL_IDENT | PCI_FILL_BASES |<br>- PCI_FILL_CLASS);<br>-<br>+ PCI_FILL_CLASS);<br> if (ahci->vendor_id != PCI_VENDOR_ID_INTEL ||<br>- ahci->device_class != PCI_CLASS_STORAGE_SATA)<br>+ (ahci->device_class != PCI_CLASS_STORAGE_SATA &&<br>+ ahci->device_class != PCI_CLASS_STORAGE_RAID))<br> ahci = NULL;<br>+ }<br>+<br>+ if (sb->device_id == PCI_DEVICE_ID_INTEL_WELLSBURG) {<br>+ ahci2 = pci_get_dev(pacc, 0, 0, 0x11, 4);<br>+ pci_fill_info(ahci2, PCI_FILL_IDENT | PCI_FILL_BASES |<br>+ PCI_FILL_CLASS);<br> }<br> <br> id = cpuid(1);<br>@@ -573,11 +586,14 @@<br> <br> if (dump_ahci) {<br> print_ahci(ahci);<br>+ print_ahci(ahci2);<br> }<br> <br> /* Clean up */<br> if (ahci)<br> pci_free_dev(ahci);<br>+ if (ahci2)<br>+ pci_free_dev(ahci2);<br> if (gfx)<br> pci_free_dev(gfx);<br> pci_free_dev(nb);<br>diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h<br>index e463260..73ebe04 100644<br>--- a/util/inteltool/inteltool.h<br>+++ b/util/inteltool/inteltool.h<br>@@ -140,6 +140,7 @@<br> #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5<br> #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102<br> #define PCI_DEVICE_ID_INTEL_CM236 0xa150<br>+#define PCI_DEVICE_ID_INTEL_WELLSBURG 0x8d47<br> #define PCI_DEVICE_ID_INTEL_82810 0x7120<br> #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122<br> #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124<br>@@ -204,6 +205,7 @@<br> #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */<br> #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */<br> #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */<br>+#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E 0x2f00 /* Haswell (Extreme) */<br> #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */<br> #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */<br> #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */<br>diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c<br>index 67b0e19..e825662 100644<br>--- a/util/inteltool/pcie.c<br>+++ b/util/inteltool/pcie.c<br>@@ -171,6 +171,24 @@<br> /* ... - Reserved */<br> };<br> <br>+static const io_register_t haswell_e_dmi_registers[] = {<br>+ { 0x10, 4, "DMIVC0RCAP" }, //DMI VC0 Resource Capability<br>+ { 0x14, 4, "DMIVC0RCTL" }, //DMI VC0 Resource Control<br>+ { 0x1a, 2, "DMIVC0RSTS" }, //DMI VC0 Resource Status<br>+ { 0x1c, 4, "DMIVC1RCAP" }, //DMI VC1 Resource Capability<br>+ { 0x20, 4, "DMIVC1RCTL" }, //DMI VC1 Resource Control<br>+ { 0x26, 2, "DMIVC1RSTS" }, //DMI VC1 Resource Status<br>+ { 0x28, 4, "DMIVCPRCAP" }, //DMI VCP Resource Capability<br>+ { 0x2c, 4, "DMIVCPRCTL" }, //DMI VCP Resource Control<br>+ { 0x32, 2, "DMIVCPRSTS" }, //DMI VCP Resource Status<br>+ { 0x34, 4, "DMIVCMRCAP" }, //DMI VCM Resource Capability<br>+ { 0x38, 4, "DMIVCMRCTL" }, //DMI VCM Resource Control<br>+ { 0x3e, 2, "DMIVCMRSTS" }, //DMI VCM Resource Status<br>+ { 0x60, 4, "DMIVC1CDTTHROTTLE" }, //DMI VC1 Credit Throttle<br>+ { 0x64, 4, "DMIVCPCDTTHROTTLE" }, //DMI VCP Credit Throttle<br>+ { 0x68, 4, "DMIVCMCDTTHROTTLE" }, //DMI VCM Credit Throttle<br>+};<br>+<br> /*<br> * Egress Port Root Complex MMIO configuration space<br> */<br>@@ -335,7 +353,11 @@<br> dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;<br> dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */<br> break;<br>-<br>+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E: //DMIRCBAR<br>+ dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;<br>+ dmi_registers = haswell_e_dmi_registers;<br>+ size = ARRAY_SIZE(haswell_e_dmi_registers);<br>+ break;<br> default:<br> printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");<br> return 1;<br>diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c<br>index f022904..de03393 100644<br>--- a/util/inteltool/powermgt.c<br>+++ b/util/inteltool/powermgt.c<br>@@ -73,7 +73,8 @@<br> { 0x52, 2, "RESERVED" },<br> { 0x54, 4, "RESERVED" },<br> { 0x58, 4, "RESERVED" },<br>- { 0x5c, 4, "RESERVED" },<br>+ { 0x5c, 2, "ALT_GPI_SMI_EN2" },<br>+ { 0x5e, 2, "ALT_GPI_SMI_STS2" },<br> /* The TCO registers start here. */<br> { 0x60, 2, "TCO_RLD" },<br> { 0x62, 1, "TCO_DAT_IN" },<br>@@ -730,6 +731,7 @@<br> case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:<br> case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:<br> case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:<br>+ case PCI_DEVICE_ID_INTEL_WELLSBURG:<br> pmbase = pci_read_word(sb, 0x40) & 0xff80;<br> pm_registers = pch_pm_registers;<br> size = ARRAY_SIZE(pch_pm_registers);<br>diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c<br>index 2ad3410..629df1c 100644<br>--- a/util/inteltool/rootcmplx.c<br>+++ b/util/inteltool/rootcmplx.c<br>@@ -97,6 +97,7 @@<br> case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:<br> case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:<br> case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:<br>+ case PCI_DEVICE_ID_INTEL_WELLSBURG:<br> rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;<br> break;<br> case PCI_DEVICE_ID_INTEL_ICH:<br>diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c<br>index cda8667..0300f2a 100644<br>--- a/util/inteltool/spi.c<br>+++ b/util/inteltool/spi.c<br>@@ -48,8 +48,8 @@<br> { 0x7c, 4, "FPR0 Flash Protected Range 2" },<br> { 0x80, 4, "FPR0 Flash Protected Range 3" },<br> { 0x84, 4, "FPR0 Flash Protected Range 4" },<br>- { 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },<br>- { 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },<br>+ { 0x90, 1, "SSFS - Software Sequencing Flash Status" },<br>+ { 0x91, 3, "SSFC - Software Sequencing Flash Control" },<br> { 0x94, 2, "PREOP - Prefix opcode Configuration" },<br> { 0x96, 2, "OPTYPE - Opcode Type Configuration" },<br> { 0x98, 8, "OPMENU - Opcode Menu Configuration" },<br>@@ -130,6 +130,7 @@<br> case PCI_DEVICE_ID_INTEL_PM55:<br> case PCI_DEVICE_ID_INTEL_QM57:<br> case PCI_DEVICE_ID_INTEL_QS57:<br>+ case PCI_DEVICE_ID_INTEL_WELLSBURG:<br> bios_cntl = pci_read_byte(sb, 0xdc);<br> bios_cntl_register = pch_bios_cntl_registers;<br> size = ARRAY_SIZE(pch_bios_cntl_registers);<br>@@ -243,6 +244,7 @@<br> case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:<br> case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:<br> case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:<br>+ case PCI_DEVICE_ID_INTEL_WELLSBURG:<br> spibaroffset = ICH9_SPIBAR;<br> rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;<br> size = ARRAY_SIZE(spi_bar_registers);<br></pre><p>To view, visit <a href="https://review.coreboot.org/20669">change 20669</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I73d289b9fc2064ba53dd0395680523be72adf490 </div>
<div style="display:none"> Gerrit-Change-Number: 20669 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Omar Pakker </div>