[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: LPC Common code
Ravishankar Sarawadi (Code Review)
gerrit at coreboot.org
Thu Jul 20 01:40:13 CEST 2017
Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/20659
Change subject: soc/intel/common/block: LPC Common code
......................................................................
soc/intel/common/block: LPC Common code
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollolake soc. Update existing Apollolake
mainboard varients {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
M src/mainboard/google/reef/bootblock.c
M src/mainboard/google/reef/ec.c
M src/mainboard/intel/leafhill/bootblock.c
M src/mainboard/intel/minnow3/bootblock.c
M src/mainboard/siemens/mc_apl1/bootblock.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/apollolake/romstage.c
R src/soc/intel/common/block/include/intelblocks/lpc.h
A src/soc/intel/common/block/lpc/Kconfig
A src/soc/intel/common/block/lpc/Makefile.inc
A src/soc/intel/common/block/lpc/lpc.c
R src/soc/intel/common/block/lpc/lpc_lib.c
15 files changed, 225 insertions(+), 181 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/20659/1
diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c
index 57d20d9..73a96c5 100644
--- a/src/mainboard/google/reef/bootblock.c
+++ b/src/mainboard/google/reef/bootblock.c
@@ -16,7 +16,7 @@
#include <baseboard/variants.h>
#include <bootblock_common.h>
#include <ec/ec.h>
-#include <soc/lpc.h>
+#include <intelblocks/lpc.h>
#include <soc/gpio.h>
#include <variant/ec.h>
diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c
index 646216b..9ea6a85 100644
--- a/src/mainboard/google/reef/ec.c
+++ b/src/mainboard/google/reef/ec.c
@@ -17,8 +17,8 @@
#include <console/console.h>
#include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
+#include <intelblocks/lpc.h>
#include <rules.h>
-#include <soc/lpc.h>
#include <variant/ec.h>
static void ramstage_ec_init(void)
diff --git a/src/mainboard/intel/leafhill/bootblock.c b/src/mainboard/intel/leafhill/bootblock.c
index 3de44a8..f71ed5e 100644
--- a/src/mainboard/intel/leafhill/bootblock.c
+++ b/src/mainboard/intel/leafhill/bootblock.c
@@ -14,7 +14,7 @@
*/
#include <bootblock_common.h>
-#include <soc/lpc.h>
+#include <intelblocks/lpc.h>
void bootblock_mainboard_init(void)
{
diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c
index b8da814..8a2e560 100644
--- a/src/mainboard/intel/minnow3/bootblock.c
+++ b/src/mainboard/intel/minnow3/bootblock.c
@@ -14,7 +14,7 @@
*/
#include <bootblock_common.h>
-#include <soc/lpc.h>
+#include <intelblocks/lpc.h>
#include "gpio.h"
void bootblock_mainboard_init(void)
diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c
index 3de44a8..f71ed5e 100644
--- a/src/mainboard/siemens/mc_apl1/bootblock.c
+++ b/src/mainboard/siemens/mc_apl1/bootblock.c
@@ -14,7 +14,7 @@
*/
#include <bootblock_common.h>
-#include <soc/lpc.h>
+#include <intelblocks/lpc.h>
void bootblock_mainboard_init(void)
{
diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c
index f077c14..de27840 100644
--- a/src/mainboard/siemens/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/mainboard.c
@@ -14,14 +14,14 @@
* GNU General Public License for more details.
*/
+#include <console/console.h>
#include <device/pci.h>
#include <device/device.h>
-#include <console/console.h>
-#include <soc/lpc.h>
-#include <soc/pci_devs.h>
-#include <string.h>
#include <hwilib.h>
#include <i210.h>
+#include <intelblocks/lpc.h>
+#include <soc/pci_devs.h>
+#include <string.h>
#include "brd_gpio.h"
#include "ptn3460.h"
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index fdbd6d7..8aaf12c 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -63,6 +63,7 @@
select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C
+ select SOC_INTEL_COMMON_BLOCK_LPC
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index bf445e5..ff05fb5 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -14,7 +14,6 @@
bootblock-y += gpio_apl.c
bootblock-y += heci.c
bootblock-y += i2c.c
-bootblock-y += lpc_lib.c
bootblock-y += mmap_boot.c
bootblock-y += pmutil.c
bootblock-y += spi.c
@@ -27,7 +26,6 @@
romstage-y += heci.c
romstage-y += i2c.c
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
-romstage-y += lpc_lib.c
romstage-y += memmap.c
romstage-y += meminit.c
romstage-y += mmap_boot.c
@@ -54,7 +52,6 @@
ramstage-y += i2c.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
ramstage-y += lpc.c
-ramstage-y += lpc_lib.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
ramstage-y += p2sb.c
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 67c87b1..2bece8b 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015-2016 Intel Corp.
- * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ * Copyright (C) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,31 +19,50 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelblocks/lpc.h>
+#include <intelblocks/rtc.h>
#include <pc80/mc146818rtc.h>
-#include <soc/acpi.h>
-#include <soc/lpc.h>
+#include <soc/gpio.h>
+#include <soc/pcr_ids.h>
#include <soc/pm.h>
#include <vboot/vbnv.h>
-
#include "chip.h"
-/*
- * SCOPE:
- * The purpose of this driver is to eliminate manual resource allocation for
- * devices under the LPC bridge.
- *
- * BACKGROUND:
- * The resource allocator reserves IO and memory resources to devices on the
- * LPC bus, but it is up to the hardware driver to make sure that those
- * resources are decoded to the LPC bus. This is what this driver does.
- *
- * THEORY OF OPERATION:
- * The .scan_bus member of the driver's ops will scan the static device tree
- * (devicetree.cb) and invoke drivers of devices on the LPC bus. This creates
- * a list of child devices, along with their resources. set_child_resources()
- * parses that list and looks for resources needed by the child devices. It
- * opens up IO and memory windows as needed.
- */
+static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = {
+ { 0xfed40000, 0x8000 },
+ { 0xfedc0000, 0x4000 },
+ { 0xfed20800, 16 },
+ { 0xfed20880, 8 },
+ { 0xfed208e0, 16 },
+ { 0xfed208f0, 8 },
+ { 0xfed30800, 16 },
+ { 0xfed30880, 8 },
+ { 0xfed308e0, 16 },
+ { 0xfed308f0, 8 },
+ { 0, 0 }
+};
+
+const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
+{
+ return apl_lpc_fixed_mmio_ranges;
+}
+
+static const struct pad_config lpc_gpios[] = {
+ PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
+};
+
+void lpc_configure_pads(void)
+{
+ gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
+}
static void rtc_init(void)
{
@@ -65,7 +83,7 @@
cmos_init(rtc_fail);
}
-static void lpc_init(struct device *dev)
+void lpc_init(struct device *dev)
{
uint8_t scnt;
struct soc_intel_apollolake_config *cfg;
@@ -87,93 +105,3 @@
/* Initialize RTC */
rtc_init();
}
-
-static void soc_lpc_add_io_resources(device_t dev)
-{
- struct resource *res;
-
- /* Add the default claimed legacy IO range for the LPC device. */
- res = new_resource(dev, 0);
- res->base = 0;
- res->size = 0x1000;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void soc_lpc_read_resources(device_t dev)
-{
- /* Get the PCI resources of this device. */
- pci_dev_read_resources(dev);
-
- /* Add IO resources to LPC. */
- soc_lpc_add_io_resources(dev);
-}
-
-static void set_child_resources(struct device *dev);
-
-static void loop_resources(struct device *dev)
-{
- struct resource *res;
-
- for (res = dev->resource_list; res; res = res->next) {
-
- if (res->flags & IORESOURCE_IO)
- lpc_open_pmio_window(res->base, res->size);
-
- if (res->flags & IORESOURCE_MEM) {
- /* Check if this is already decoded. */
- if (lpc_fits_fixed_mmio_window(res->base, res->size))
- continue;
-
- lpc_open_mmio_window(res->base, res->size);
- }
-
- }
- set_child_resources(dev);
-}
-
-/*
- * Loop through all the child devices' resources, and open up windows to the
- * LPC bus, as appropriate.
- */
-static void set_child_resources(struct device *dev)
-{
- struct bus *link;
- struct device *child;
-
- for (link = dev->link_list; link; link = link->next) {
- for (child = link->children; child; child = child->sibling)
- loop_resources(child);
- }
-}
-
-static void set_resources(device_t dev)
-{
- pci_dev_set_resources(dev);
-
- /* Close all previously opened windows and allocate from scratch. */
- lpc_close_pmio_windows();
- /* Now open up windows to devices which have declared resources. */
- set_child_resources(dev);
-}
-
-static struct device_operations device_ops = {
- .read_resources = &soc_lpc_read_resources,
- .set_resources = set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .write_acpi_tables = southbridge_write_acpi_tables,
- .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
- .init = lpc_init,
- .scan_bus = scan_lpc_bus,
-};
-
-static const unsigned short pci_device_ids[] = {
- PCI_DEVICE_ID_INTEL_APL_LPC,
- PCI_DEVICE_ID_INTEL_GLK_LPC,
- 0,
-};
-
-static const struct pci_driver soc_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = pci_device_ids,
-};
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 7c9268a..8894722 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -28,6 +28,7 @@
#include <cpu/x86/mtrr.h>
#include <device/pci_def.h>
#include <device/resource.h>
+#include <intelblocks/lpc.h>
#include <fsp/api.h>
#include <fsp/memmap.h>
#include <fsp/util.h>
@@ -37,7 +38,6 @@
#include <soc/cpu.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
-#include <soc/lpc.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/common/block/include/intelblocks/lpc.h
similarity index 69%
rename from src/soc/intel/apollolake/include/soc/lpc.h
rename to src/soc/intel/common/block/include/intelblocks/lpc.h
index da918a1..486839c 100644
--- a/src/soc/intel/apollolake/include/soc/lpc.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc.h
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ * Copyright (C) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,15 +14,15 @@
* GNU General Public License for more details.
*/
-#ifndef _SOC_APOLLOLAKE_LPC_H_
-#define _SOC_APOLLOLAKE_LPC_H_
+#ifndef _SOC_COMMON_BLOCK_LPC_H_
+#define _SOC_COMMON_BLOCK_LPC_H_
#include <stddef.h>
#include <stdint.h>
#define REG_SERIRQ_CTL 0x64
-#define SCNT_EN (1 << 7)
-#define SCNT_MODE (1 << 6)
+#define SCNT_EN (1 << 7)
+#define SCNT_MODE (1 << 6)
/*
* IO decode enable macros are in the format IO_<peripheral>_<IO port>.
@@ -41,23 +40,29 @@
#define IOE_KBC_60_64 (1 << 10)
#define IOE_HGE_208 (1 << 9)
#define IOE_LGE_200 (1 << 8)
-#define IOE_FDD_EN (1 << 3)
-#define IOE_LPT_EN (1 << 2)
+#define IOE_FDD_EN (1 << 3)
+#define IOE_LPT_EN (1 << 2)
#define IOE_COMB_EN (1 << 1)
#define IOE_COMA_EN (1 << 0)
#define REG_GENERIC_IO_RANGE(n) ((((n) & 0x3) * 4) + 0x84)
#define LGIR_AMASK_MASK (0xfc << 16)
#define LGIR_ADDR_MASK 0xfffc
-#define LGIR_EN (1 << 0)
-#define LGIR_MAX_WINDOW_SIZE 256
-#define NUM_GENERIC_IO_RANGES 4
-#define REG_GENERIC_MEM_RANGE 0x98
+#define LGIR_EN (1 << 0)
+#define LGIR_MAX_WINDOW_SIZE 256
+#define NUM_GENERIC_IO_RANGES 4
+#define REG_GENERIC_MEM_RANGE 0x98
#define LGMR_ADDR_MASK 0xffff0000
-#define LGMR_EN (1 << 0)
+#define LGMR_EN (1 << 0)
#define LGMR_WINDOW_SIZE (64 * KiB)
-/* Configure the SOC's LPC pads and mux them to the LPC function. */
-void lpc_configure_pads(void);
+#define REG_BIOS_CNTL 0xdc
+#define LPC_BC_BILD (1 << 7) /* BILD */
+#define LPC_BC_LE (1 << 2) /* LE */
+#define LPC_BC_EISS (1 << 5) /* EISS */
+
+#define REG_PCCTL 0xE0 /* PCI Clock Control */
+#define CLKRUN_EN (1 << 0)
+
/* Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together. */
void lpc_enable_fixed_io_ranges(uint16_t io_enables);
/* Open a generic IO window to the LPC bus. Four windows are available. */
@@ -68,5 +73,17 @@
void lpc_open_mmio_window(uintptr_t base, size_t size);
/* Returns true if given window is decoded to LPC via a fixed range. */
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
+/* Init SoC Spcific LPC features. Common definition will be weak and
+each soc will need to define the init.*/
+void lpc_init(struct device *dev);
+/* Init LPC GPIO pads */
+void lpc_configure_pads(void);
+/* Get SoC speicific MMIO ranges */
+const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void);
-#endif /* _SOC_APOLLOLAKE_LPC_H_ */
+struct lpc_mmio_range {
+ uintptr_t base;
+ size_t size;
+};
+
+#endif /* _SOC_COMMON_BLOCK_LPC_H_ */
diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig
new file mode 100644
index 0000000..a5eab72
--- /dev/null
+++ b/src/soc/intel/common/block/lpc/Kconfig
@@ -0,0 +1,5 @@
+config SOC_INTEL_COMMON_BLOCK_LPC
+ bool
+ help
+ Use common LPC code for platform. Only soc specific code needs to
+ be implemented per requirement.
diff --git a/src/soc/intel/common/block/lpc/Makefile.inc b/src/soc/intel/common/block/lpc/Makefile.inc
new file mode 100644
index 0000000..1d6b3fd
--- /dev/null
+++ b/src/soc/intel/common/block/lpc/Makefile.inc
@@ -0,0 +1,7 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c
+
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c
+
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
new file mode 100644
index 0000000..6528239
--- /dev/null
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/lpc.h>
+#include <soc/acpi.h>
+#include <soc/pm.h>
+
+/*Common weak definition, needs to be implemented in each soc LPC driver*/
+__attribute__((weak)) void lpc_init(struct device *dev) { /* no-op */ }
+
+static void soc_lpc_add_io_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Add the default claimed legacy IO range for the LPC device. */
+ res = new_resource(dev, 0);
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void soc_lpc_read_resources(device_t dev)
+{
+ /* Get the PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add IO resources to LPC. */
+ soc_lpc_add_io_resources(dev);
+}
+
+static void set_child_resources(struct device *dev);
+
+static void loop_resources(struct device *dev)
+{
+ struct resource *res;
+
+ for (res = dev->resource_list; res; res = res->next) {
+ if (res->flags & IORESOURCE_IO)
+ lpc_open_pmio_window(res->base, res->size);
+
+ if (res->flags & IORESOURCE_MEM) {
+ /* Check if this is already decoded. */
+ if (lpc_fits_fixed_mmio_window(res->base, res->size))
+ continue;
+
+ lpc_open_mmio_window(res->base, res->size);
+ }
+ }
+ set_child_resources(dev);
+}
+
+/*
+ * Loop through all the child devices' resources, and open up windows to the
+ * LPC bus, as appropriate.
+ */
+static void set_child_resources(struct device *dev)
+{
+ struct bus *link;
+ struct device *child;
+
+ for (link = dev->link_list; link; link = link->next) {
+ for (child = link->children; child; child = child->sibling)
+ loop_resources(child);
+ }
+}
+
+static void set_resources(device_t dev)
+{
+ pci_dev_set_resources(dev);
+
+ /* Now open up windows to devices which have declared resources. */
+ set_child_resources(dev);
+}
+
+static struct device_operations device_ops = {
+ .read_resources = soc_lpc_read_resources,
+ .set_resources = set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .write_acpi_tables = southbridge_write_acpi_tables,
+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+ .init = lpc_init,
+ .scan_bus = scan_lpc_bus,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE,
+ PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE,
+ PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM,
+ PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM,
+ PCI_DEVICE_ID_INTEL_KBP_H_C236,
+ PCI_DEVICE_ID_INTEL_KBP_H_PREMIUM,
+ PCI_DEVICE_ID_INTEL_KBP_H_QM170,
+ PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22,
+ PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22,
+ PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU,
+ PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM,
+ PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM,
+ PCI_DEVICE_ID_INTEL_APL_LPC,
+ PCI_DEVICE_ID_INTEL_GLK_LPC,
+ 0
+};
+
+static const struct pci_driver soc_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
similarity index 79%
rename from src/soc/intel/apollolake/lpc_lib.c
rename to src/soc/intel/common/block/lpc/lpc_lib.c
index 08c16a7..77fb19f 100644
--- a/src/soc/intel/apollolake/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -19,48 +19,11 @@
#include <console/console.h>
#include <device/pci.h>
+#include <intelblocks/lpc.h>
#include <lib.h>
-#include <soc/gpio.h>
-#include <soc/lpc.h>
#include <soc/pci_devs.h>
-/*
- * These are MMIO ranges that the silicon designers decided are always going to
- * be decoded to LPC.
- */
-static const struct lpc_mmio_range {
- uintptr_t base;
- size_t size;
-} lpc_fixed_mmio_ranges[] = {
- { 0xfed40000, 0x8000 },
- { 0xfedc0000, 0x4000 },
- { 0xfed20800, 16 },
- { 0xfed20880, 8 },
- { 0xfed208e0, 16 },
- { 0xfed208f0, 8 },
- { 0xfed30800, 16 },
- { 0xfed30880, 8 },
- { 0xfed308e0, 16 },
- { 0xfed308f0, 8 },
- { 0, 0 }
-};
-
-static const struct pad_config lpc_gpios[] = {
- PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
- PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
- PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
- PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
- PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
- PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
- PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
- PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
- PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
-};
-
-void lpc_configure_pads(void)
-{
- gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
-}
+__attribute__((weak)) void lpc_configure_pads(void) { /* no-op */ }
void lpc_enable_fixed_io_ranges(uint16_t io_enables)
{
@@ -172,6 +135,8 @@
{
resource_t res_end, range_end;
const struct lpc_mmio_range *range;
+ const struct lpc_mmio_range *lpc_fixed_mmio_ranges =
+ soc_get_fixed_mmio_ranges();
for (range = lpc_fixed_mmio_ranges; range->size; range++) {
range_end = range->base + range->size;
@@ -187,3 +152,4 @@
}
return false;
}
+
--
To view, visit https://review.coreboot.org/20659
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Gerrit-Change-Number: 20659
Gerrit-PatchSet: 1
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
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