<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20659">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: LPC Common code<br><br>Add LPC common code to be shared across Intel platforms.<br>Also add LPC library functions to be shared across platforms.<br><br>Use common LPC code for Apollolake soc. Update existing Apollolake<br>mainboard varients {google,intel,siemens} to use new common<br>LPC header file.<br><br>Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/mainboard/google/reef/bootblock.c<br>M src/mainboard/google/reef/ec.c<br>M src/mainboard/intel/leafhill/bootblock.c<br>M src/mainboard/intel/minnow3/bootblock.c<br>M src/mainboard/siemens/mc_apl1/bootblock.c<br>M src/mainboard/siemens/mc_apl1/mainboard.c<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/apollolake/Makefile.inc<br>M src/soc/intel/apollolake/lpc.c<br>M src/soc/intel/apollolake/romstage.c<br>R src/soc/intel/common/block/include/intelblocks/lpc.h<br>A src/soc/intel/common/block/lpc/Kconfig<br>A src/soc/intel/common/block/lpc/Makefile.inc<br>A src/soc/intel/common/block/lpc/lpc.c<br>R src/soc/intel/common/block/lpc/lpc_lib.c<br>15 files changed, 225 insertions(+), 181 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/20659/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c<br>index 57d20d9..73a96c5 100644<br>--- a/src/mainboard/google/reef/bootblock.c<br>+++ b/src/mainboard/google/reef/bootblock.c<br>@@ -16,7 +16,7 @@<br> #include <baseboard/variants.h><br> #include <bootblock_common.h><br> #include <ec/ec.h><br>-#include <soc/lpc.h><br>+#include <intelblocks/lpc.h><br> #include <soc/gpio.h><br> #include <variant/ec.h><br> <br>diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c<br>index 646216b..9ea6a85 100644<br>--- a/src/mainboard/google/reef/ec.c<br>+++ b/src/mainboard/google/reef/ec.c<br>@@ -17,8 +17,8 @@<br> #include <console/console.h><br> #include <ec/ec.h><br> #include <ec/google/chromeec/ec.h><br>+#include <intelblocks/lpc.h><br> #include <rules.h><br>-#include <soc/lpc.h><br> #include <variant/ec.h><br> <br> static void ramstage_ec_init(void)<br>diff --git a/src/mainboard/intel/leafhill/bootblock.c b/src/mainboard/intel/leafhill/bootblock.c<br>index 3de44a8..f71ed5e 100644<br>--- a/src/mainboard/intel/leafhill/bootblock.c<br>+++ b/src/mainboard/intel/leafhill/bootblock.c<br>@@ -14,7 +14,7 @@<br> */<br> <br> #include <bootblock_common.h><br>-#include <soc/lpc.h><br>+#include <intelblocks/lpc.h><br> <br> void bootblock_mainboard_init(void)<br> {<br>diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c<br>index b8da814..8a2e560 100644<br>--- a/src/mainboard/intel/minnow3/bootblock.c<br>+++ b/src/mainboard/intel/minnow3/bootblock.c<br>@@ -14,7 +14,7 @@<br> */<br> <br> #include <bootblock_common.h><br>-#include <soc/lpc.h><br>+#include <intelblocks/lpc.h><br> #include "gpio.h"<br> <br> void bootblock_mainboard_init(void)<br>diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c<br>index 3de44a8..f71ed5e 100644<br>--- a/src/mainboard/siemens/mc_apl1/bootblock.c<br>+++ b/src/mainboard/siemens/mc_apl1/bootblock.c<br>@@ -14,7 +14,7 @@<br> */<br> <br> #include <bootblock_common.h><br>-#include <soc/lpc.h><br>+#include <intelblocks/lpc.h><br> <br> void bootblock_mainboard_init(void)<br> {<br>diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c<br>index f077c14..de27840 100644<br>--- a/src/mainboard/siemens/mc_apl1/mainboard.c<br>+++ b/src/mainboard/siemens/mc_apl1/mainboard.c<br>@@ -14,14 +14,14 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <console/console.h><br> #include <device/pci.h><br> #include <device/device.h><br>-#include <console/console.h><br>-#include <soc/lpc.h><br>-#include <soc/pci_devs.h><br>-#include <string.h><br> #include <hwilib.h><br> #include <i210.h><br>+#include <intelblocks/lpc.h><br>+#include <soc/pci_devs.h><br>+#include <string.h><br> #include "brd_gpio.h"<br> #include "ptn3460.h"<br> <br>diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig<br>index fdbd6d7..8aaf12c 100644<br>--- a/src/soc/intel/apollolake/Kconfig<br>+++ b/src/soc/intel/apollolake/Kconfig<br>@@ -63,6 +63,7 @@<br> select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY<br> select SOC_INTEL_COMMON_BLOCK_ITSS<br> select SOC_INTEL_COMMON_BLOCK_I2C<br>+ select SOC_INTEL_COMMON_BLOCK_LPC<br> select SOC_INTEL_COMMON_BLOCK_LPSS<br> select SOC_INTEL_COMMON_BLOCK_PCR<br> select SOC_INTEL_COMMON_BLOCK_RTC<br>diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc<br>index bf445e5..ff05fb5 100644<br>--- a/src/soc/intel/apollolake/Makefile.inc<br>+++ b/src/soc/intel/apollolake/Makefile.inc<br>@@ -14,7 +14,6 @@<br> bootblock-y += gpio_apl.c<br> bootblock-y += heci.c<br> bootblock-y += i2c.c<br>-bootblock-y += lpc_lib.c<br> bootblock-y += mmap_boot.c<br> bootblock-y += pmutil.c<br> bootblock-y += spi.c<br>@@ -27,7 +26,6 @@<br> romstage-y += heci.c<br> romstage-y += i2c.c<br> romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br>-romstage-y += lpc_lib.c<br> romstage-y += memmap.c<br> romstage-y += meminit.c<br> romstage-y += mmap_boot.c<br>@@ -54,7 +52,6 @@<br> ramstage-y += i2c.c<br> ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br> ramstage-y += lpc.c<br>-ramstage-y += lpc_lib.c<br> ramstage-y += memmap.c<br> ramstage-y += mmap_boot.c<br> ramstage-y += p2sb.c<br>diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c<br>index 67c87b1..2bece8b 100644<br>--- a/src/soc/intel/apollolake/lpc.c<br>+++ b/src/soc/intel/apollolake/lpc.c<br>@@ -1,8 +1,7 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2015-2016 Intel Corp.<br>- * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)<br>+ * Copyright (C) 2017 Intel Corp.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -20,31 +19,50 @@<br> #include <device/device.h><br> #include <device/pci.h><br> #include <device/pci_ids.h><br>+#include <intelblocks/lpc.h><br>+#include <intelblocks/rtc.h><br> #include <pc80/mc146818rtc.h><br>-#include <soc/acpi.h><br>-#include <soc/lpc.h><br>+#include <soc/gpio.h><br>+#include <soc/pcr_ids.h><br> #include <soc/pm.h><br> #include <vboot/vbnv.h><br>-<br> #include "chip.h"<br> <br>-/*<br>- * SCOPE:<br>- * The purpose of this driver is to eliminate manual resource allocation for<br>- * devices under the LPC bridge.<br>- *<br>- * BACKGROUND:<br>- * The resource allocator reserves IO and memory resources to devices on the<br>- * LPC bus, but it is up to the hardware driver to make sure that those<br>- * resources are decoded to the LPC bus. This is what this driver does.<br>- *<br>- * THEORY OF OPERATION:<br>- * The .scan_bus member of the driver's ops will scan the static device tree<br>- * (devicetree.cb) and invoke drivers of devices on the LPC bus. This creates<br>- * a list of child devices, along with their resources. set_child_resources()<br>- * parses that list and looks for resources needed by the child devices. It<br>- * opens up IO and memory windows as needed.<br>- */<br>+static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = {<br>+ { 0xfed40000, 0x8000 },<br>+ { 0xfedc0000, 0x4000 },<br>+ { 0xfed20800, 16 },<br>+ { 0xfed20880, 8 },<br>+ { 0xfed208e0, 16 },<br>+ { 0xfed208f0, 8 },<br>+ { 0xfed30800, 16 },<br>+ { 0xfed30880, 8 },<br>+ { 0xfed308e0, 16 },<br>+ { 0xfed308f0, 8 },<br>+ { 0, 0 }<br>+};<br>+<br>+const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)<br>+{<br>+ return apl_lpc_fixed_mmio_ranges;<br>+}<br>+<br>+static const struct pad_config lpc_gpios[] = {<br>+ PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),<br>+ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),<br>+ PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),<br>+ PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),<br>+ PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),<br>+ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),<br>+ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),<br>+ PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),<br>+ PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)<br>+};<br>+<br>+void lpc_configure_pads(void)<br>+{<br>+ gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));<br>+}<br> <br> static void rtc_init(void)<br> {<br>@@ -65,7 +83,7 @@<br> cmos_init(rtc_fail);<br> }<br> <br>-static void lpc_init(struct device *dev)<br>+void lpc_init(struct device *dev)<br> {<br> uint8_t scnt;<br> struct soc_intel_apollolake_config *cfg;<br>@@ -87,93 +105,3 @@<br> /* Initialize RTC */<br> rtc_init();<br> }<br>-<br>-static void soc_lpc_add_io_resources(device_t dev)<br>-{<br>- struct resource *res;<br>-<br>- /* Add the default claimed legacy IO range for the LPC device. */<br>- res = new_resource(dev, 0);<br>- res->base = 0;<br>- res->size = 0x1000;<br>- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-}<br>-<br>-static void soc_lpc_read_resources(device_t dev)<br>-{<br>- /* Get the PCI resources of this device. */<br>- pci_dev_read_resources(dev);<br>-<br>- /* Add IO resources to LPC. */<br>- soc_lpc_add_io_resources(dev);<br>-}<br>-<br>-static void set_child_resources(struct device *dev);<br>-<br>-static void loop_resources(struct device *dev)<br>-{<br>- struct resource *res;<br>-<br>- for (res = dev->resource_list; res; res = res->next) {<br>-<br>- if (res->flags & IORESOURCE_IO)<br>- lpc_open_pmio_window(res->base, res->size);<br>-<br>- if (res->flags & IORESOURCE_MEM) {<br>- /* Check if this is already decoded. */<br>- if (lpc_fits_fixed_mmio_window(res->base, res->size))<br>- continue;<br>-<br>- lpc_open_mmio_window(res->base, res->size);<br>- }<br>-<br>- }<br>- set_child_resources(dev);<br>-}<br>-<br>-/*<br>- * Loop through all the child devices' resources, and open up windows to the<br>- * LPC bus, as appropriate.<br>- */<br>-static void set_child_resources(struct device *dev)<br>-{<br>- struct bus *link;<br>- struct device *child;<br>-<br>- for (link = dev->link_list; link; link = link->next) {<br>- for (child = link->children; child; child = child->sibling)<br>- loop_resources(child);<br>- }<br>-}<br>-<br>-static void set_resources(device_t dev)<br>-{<br>- pci_dev_set_resources(dev);<br>-<br>- /* Close all previously opened windows and allocate from scratch. */<br>- lpc_close_pmio_windows();<br>- /* Now open up windows to devices which have declared resources. */<br>- set_child_resources(dev);<br>-}<br>-<br>-static struct device_operations device_ops = {<br>- .read_resources = &soc_lpc_read_resources,<br>- .set_resources = set_resources,<br>- .enable_resources = &pci_dev_enable_resources,<br>- .write_acpi_tables = southbridge_write_acpi_tables,<br>- .acpi_inject_dsdt_generator = southbridge_inject_dsdt,<br>- .init = lpc_init,<br>- .scan_bus = scan_lpc_bus,<br>-};<br>-<br>-static const unsigned short pci_device_ids[] = {<br>- PCI_DEVICE_ID_INTEL_APL_LPC,<br>- PCI_DEVICE_ID_INTEL_GLK_LPC,<br>- 0,<br>-};<br>-<br>-static const struct pci_driver soc_lpc __pci_driver = {<br>- .ops = &device_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .devices = pci_device_ids,<br>-};<br>diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c<br>index 7c9268a..8894722 100644<br>--- a/src/soc/intel/apollolake/romstage.c<br>+++ b/src/soc/intel/apollolake/romstage.c<br>@@ -28,6 +28,7 @@<br> #include <cpu/x86/mtrr.h><br> #include <device/pci_def.h><br> #include <device/resource.h><br>+#include <intelblocks/lpc.h><br> #include <fsp/api.h><br> #include <fsp/memmap.h><br> #include <fsp/util.h><br>@@ -37,7 +38,6 @@<br> #include <soc/cpu.h><br> #include <soc/intel/common/mrc_cache.h><br> #include <soc/iomap.h><br>-#include <soc/lpc.h><br> #include <soc/systemagent.h><br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br>diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/common/block/include/intelblocks/lpc.h<br>similarity index 69%<br>rename from src/soc/intel/apollolake/include/soc/lpc.h<br>rename to src/soc/intel/common/block/include/intelblocks/lpc.h<br>index da918a1..486839c 100644<br>--- a/src/soc/intel/apollolake/include/soc/lpc.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/lpc.h<br>@@ -1,8 +1,7 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2016 Intel Corp.<br>- * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)<br>+ * Copyright (C) 2017 Intel Corp.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -15,15 +14,15 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#ifndef _SOC_APOLLOLAKE_LPC_H_<br>-#define _SOC_APOLLOLAKE_LPC_H_<br>+#ifndef _SOC_COMMON_BLOCK_LPC_H_<br>+#define _SOC_COMMON_BLOCK_LPC_H_<br> <br> #include <stddef.h><br> #include <stdint.h><br> <br> #define REG_SERIRQ_CTL 0x64<br>-#define SCNT_EN (1 << 7)<br>-#define SCNT_MODE (1 << 6)<br>+#define SCNT_EN (1 << 7)<br>+#define SCNT_MODE (1 << 6)<br> <br> /*<br> * IO decode enable macros are in the format IO_<peripheral>_<IO port>.<br>@@ -41,23 +40,29 @@<br> #define IOE_KBC_60_64 (1 << 10)<br> #define IOE_HGE_208 (1 << 9)<br> #define IOE_LGE_200 (1 << 8)<br>-#define IOE_FDD_EN (1 << 3)<br>-#define IOE_LPT_EN (1 << 2)<br>+#define IOE_FDD_EN (1 << 3)<br>+#define IOE_LPT_EN (1 << 2)<br> #define IOE_COMB_EN (1 << 1)<br> #define IOE_COMA_EN (1 << 0)<br> #define REG_GENERIC_IO_RANGE(n) ((((n) & 0x3) * 4) + 0x84)<br> #define LGIR_AMASK_MASK (0xfc << 16)<br> #define LGIR_ADDR_MASK 0xfffc<br>-#define LGIR_EN (1 << 0)<br>-#define LGIR_MAX_WINDOW_SIZE 256<br>-#define NUM_GENERIC_IO_RANGES 4<br>-#define REG_GENERIC_MEM_RANGE 0x98<br>+#define LGIR_EN (1 << 0)<br>+#define LGIR_MAX_WINDOW_SIZE 256<br>+#define NUM_GENERIC_IO_RANGES 4<br>+#define REG_GENERIC_MEM_RANGE 0x98<br> #define LGMR_ADDR_MASK 0xffff0000<br>-#define LGMR_EN (1 << 0)<br>+#define LGMR_EN (1 << 0)<br> #define LGMR_WINDOW_SIZE (64 * KiB)<br> <br>-/* Configure the SOC's LPC pads and mux them to the LPC function. */<br>-void lpc_configure_pads(void);<br>+#define REG_BIOS_CNTL 0xdc<br>+#define LPC_BC_BILD (1 << 7) /* BILD */<br>+#define LPC_BC_LE (1 << 2) /* LE */<br>+#define LPC_BC_EISS (1 << 5) /* EISS */<br>+<br>+#define REG_PCCTL 0xE0 /* PCI Clock Control */<br>+#define CLKRUN_EN (1 << 0)<br>+<br> /* Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together. */<br> void lpc_enable_fixed_io_ranges(uint16_t io_enables);<br> /* Open a generic IO window to the LPC bus. Four windows are available. */<br>@@ -68,5 +73,17 @@<br> void lpc_open_mmio_window(uintptr_t base, size_t size);<br> /* Returns true if given window is decoded to LPC via a fixed range. */<br> bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);<br>+/* Init SoC Spcific LPC features. Common definition will be weak and<br>+each soc will need to define the init.*/<br>+void lpc_init(struct device *dev);<br>+/* Init LPC GPIO pads */<br>+void lpc_configure_pads(void);<br>+/* Get SoC speicific MMIO ranges */<br>+const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void);<br> <br>-#endif /* _SOC_APOLLOLAKE_LPC_H_ */<br>+struct lpc_mmio_range {<br>+ uintptr_t base;<br>+ size_t size;<br>+};<br>+<br>+#endif /* _SOC_COMMON_BLOCK_LPC_H_ */<br>diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig<br>new file mode 100644<br>index 0000000..a5eab72<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/lpc/Kconfig<br>@@ -0,0 +1,5 @@<br>+config SOC_INTEL_COMMON_BLOCK_LPC<br>+ bool<br>+ help<br>+ Use common LPC code for platform. Only soc specific code needs to<br>+ be implemented per requirement. <br>diff --git a/src/soc/intel/common/block/lpc/Makefile.inc b/src/soc/intel/common/block/lpc/Makefile.inc<br>new file mode 100644<br>index 0000000..1d6b3fd<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/lpc/Makefile.inc<br>@@ -0,0 +1,7 @@<br>+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c<br>+<br>+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c<br>+<br>+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c<br>+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c<br>+<br>diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c<br>new file mode 100644<br>index 0000000..6528239<br>--- /dev/null<br>+++ b/src/soc/intel/common/block/lpc/lpc.c<br>@@ -0,0 +1,123 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+#include <intelblocks/lpc.h><br>+#include <soc/acpi.h><br>+#include <soc/pm.h><br>+<br>+/*Common weak definition, needs to be implemented in each soc LPC driver*/<br>+__attribute__((weak)) void lpc_init(struct device *dev) { /* no-op */ }<br>+<br>+static void soc_lpc_add_io_resources(device_t dev)<br>+{<br>+ struct resource *res;<br>+<br>+ /* Add the default claimed legacy IO range for the LPC device. */<br>+ res = new_resource(dev, 0);<br>+ res->base = 0;<br>+ res->size = 0x1000;<br>+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>+}<br>+<br>+static void soc_lpc_read_resources(device_t dev)<br>+{<br>+ /* Get the PCI resources of this device. */<br>+ pci_dev_read_resources(dev);<br>+<br>+ /* Add IO resources to LPC. */<br>+ soc_lpc_add_io_resources(dev);<br>+}<br>+<br>+static void set_child_resources(struct device *dev);<br>+<br>+static void loop_resources(struct device *dev)<br>+{<br>+ struct resource *res;<br>+<br>+ for (res = dev->resource_list; res; res = res->next) {<br>+ if (res->flags & IORESOURCE_IO)<br>+ lpc_open_pmio_window(res->base, res->size);<br>+<br>+ if (res->flags & IORESOURCE_MEM) {<br>+ /* Check if this is already decoded. */<br>+ if (lpc_fits_fixed_mmio_window(res->base, res->size))<br>+ continue;<br>+<br>+ lpc_open_mmio_window(res->base, res->size);<br>+ }<br>+ }<br>+ set_child_resources(dev);<br>+}<br>+<br>+/*<br>+ * Loop through all the child devices' resources, and open up windows to the<br>+ * LPC bus, as appropriate.<br>+ */<br>+static void set_child_resources(struct device *dev)<br>+{<br>+ struct bus *link;<br>+ struct device *child;<br>+<br>+ for (link = dev->link_list; link; link = link->next) {<br>+ for (child = link->children; child; child = child->sibling)<br>+ loop_resources(child);<br>+ }<br>+}<br>+<br>+static void set_resources(device_t dev)<br>+{<br>+ pci_dev_set_resources(dev);<br>+<br>+ /* Now open up windows to devices which have declared resources. */<br>+ set_child_resources(dev);<br>+}<br>+<br>+static struct device_operations device_ops = {<br>+ .read_resources = soc_lpc_read_resources,<br>+ .set_resources = set_resources,<br>+ .enable_resources = pci_dev_enable_resources,<br>+ .write_acpi_tables = southbridge_write_acpi_tables,<br>+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,<br>+ .init = lpc_init,<br>+ .scan_bus = scan_lpc_bus,<br>+};<br>+<br>+static const unsigned short pci_device_ids[] = {<br>+ PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE,<br>+ PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE,<br>+ PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM,<br>+ PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM,<br>+ PCI_DEVICE_ID_INTEL_KBP_H_C236,<br>+ PCI_DEVICE_ID_INTEL_KBP_H_PREMIUM,<br>+ PCI_DEVICE_ID_INTEL_KBP_H_QM170,<br>+ PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22,<br>+ PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22,<br>+ PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU,<br>+ PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM,<br>+ PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM,<br>+ PCI_DEVICE_ID_INTEL_APL_LPC,<br>+ PCI_DEVICE_ID_INTEL_GLK_LPC,<br>+ 0<br>+};<br>+<br>+static const struct pci_driver soc_lpc __pci_driver = {<br>+ .ops = &device_ops,<br>+ .vendor = PCI_VENDOR_ID_INTEL,<br>+ .devices = pci_device_ids,<br>+};<br>diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c<br>similarity index 79%<br>rename from src/soc/intel/apollolake/lpc_lib.c<br>rename to src/soc/intel/common/block/lpc/lpc_lib.c<br>index 08c16a7..77fb19f 100644<br>--- a/src/soc/intel/apollolake/lpc_lib.c<br>+++ b/src/soc/intel/common/block/lpc/lpc_lib.c<br>@@ -19,48 +19,11 @@<br> <br> #include <console/console.h><br> #include <device/pci.h><br>+#include <intelblocks/lpc.h><br> #include <lib.h><br>-#include <soc/gpio.h><br>-#include <soc/lpc.h><br> #include <soc/pci_devs.h><br> <br>-/*<br>- * These are MMIO ranges that the silicon designers decided are always going to<br>- * be decoded to LPC.<br>- */<br>-static const struct lpc_mmio_range {<br>- uintptr_t base;<br>- size_t size;<br>-} lpc_fixed_mmio_ranges[] = {<br>- { 0xfed40000, 0x8000 },<br>- { 0xfedc0000, 0x4000 },<br>- { 0xfed20800, 16 },<br>- { 0xfed20880, 8 },<br>- { 0xfed208e0, 16 },<br>- { 0xfed208f0, 8 },<br>- { 0xfed30800, 16 },<br>- { 0xfed30880, 8 },<br>- { 0xfed308e0, 16 },<br>- { 0xfed308f0, 8 },<br>- { 0, 0 }<br>-};<br>-<br>-static const struct pad_config lpc_gpios[] = {<br>- PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),<br>- PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),<br>- PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),<br>- PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),<br>- PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),<br>- PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),<br>- PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),<br>- PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),<br>- PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)<br>-};<br>-<br>-void lpc_configure_pads(void)<br>-{<br>- gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));<br>-}<br>+__attribute__((weak)) void lpc_configure_pads(void) { /* no-op */ }<br> <br> void lpc_enable_fixed_io_ranges(uint16_t io_enables)<br> {<br>@@ -172,6 +135,8 @@<br> {<br> resource_t res_end, range_end;<br> const struct lpc_mmio_range *range;<br>+ const struct lpc_mmio_range *lpc_fixed_mmio_ranges =<br>+ soc_get_fixed_mmio_ranges();<br> <br> for (range = lpc_fixed_mmio_ranges; range->size; range++) {<br> range_end = range->base + range->size;<br>@@ -187,3 +152,4 @@<br> }<br> return false;<br> }<br>+<br></pre><p>To view, visit <a href="https://review.coreboot.org/20659">change 20659</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a </div>
<div style="display:none"> Gerrit-Change-Number: 20659 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>