[coreboot-gerrit] Change in coreboot[master]: x86/sse: Use compiler defined macros instead of Kconfig option
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Tue Jul 18 19:34:19 CEST 2017
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20636
Change subject: x86/sse: Use compiler defined macros instead of Kconfig option
......................................................................
x86/sse: Use compiler defined macros instead of Kconfig option
Compilers define a set of macros in case SSE has been enabled using the
-msse switch or by setting an architecture that supports SSE.
Define and use marcos to detect SSE enabled compilers.
In the next step we can get rid of CONFIG_SSE and CONFIG_SSE2.
Change-Id: I787ed37d34125ea9f8919d67f3240fdee6c689ec
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/arch/x86/assembly_entry.S
M src/arch/x86/bootblock_crt0.S
M src/arch/x86/bootblock_romcc.S
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smm_module_loader.c
A src/include/cpu/x86/sse.h
M src/lib/ramtest.c
7 files changed, 66 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/20636/1
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 220cc6e..3ab66c0 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -13,7 +13,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
+#include <cpu/x86/sse.h>
#include <rules.h>
/*
@@ -81,7 +81,7 @@
#include <arch/x86/prologue.inc>
#include <cpu/x86/32bit/entry32.inc>
#include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
+#if IS_ENABLED(COMPILER_SSE)
#include <cpu/x86/sse_enable.inc>
#endif
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S
index 1b160f4..9d10661 100644
--- a/src/arch/x86/bootblock_crt0.S
+++ b/src/arch/x86/bootblock_crt0.S
@@ -21,6 +21,7 @@
* GNU General Public License for more details.
*/
+#include <cpu/x86/sse.h>
#include <cpu/x86/cr.h>
/*
@@ -66,12 +67,12 @@
movd %edx, %mm2
#endif
-#if IS_ENABLED(CONFIG_SSE)
+#if IS_ENABLED(COMPILER_SSE)
enable_sse:
mov %cr4, %eax
or $CR4_OSFXSR, %ax
mov %eax, %cr4
-#endif /* IS_ENABLED(CONFIG_SSE) */
+#endif /* IS_ENABLED(COMPILER_SSE) */
/* We're done. Now it's up to platform-specific code */
jmp bootblock_pre_c_entry
diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S
index 6c1723a..3991e4e 100644
--- a/src/arch/x86/bootblock_romcc.S
+++ b/src/arch/x86/bootblock_romcc.S
@@ -30,6 +30,7 @@
* of the includes.
*/
+#include <cpu/x86/sse.h>
#include <arch/x86/prologue.inc>
#include <cpu/x86/16bit/entry16.inc>
#include <cpu/x86/16bit/reset16.inc>
@@ -39,7 +40,7 @@
#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
#endif
-#if IS_ENABLED(CONFIG_SSE)
+#if IS_ENABLED(COMPILER_SSE)
#include <cpu/x86/sse_enable.inc>
#endif
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index e654915..d1615c9 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -13,7 +13,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
+#include <cpu/x86/sse.h>
#include <cpu/x86/cr.h>
/* The SIPI vector is responsible for initializing the APs in the sytem. It
@@ -185,7 +185,7 @@
and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax
mov %eax, %cr0
-#if IS_ENABLED(CONFIG_SSE)
+#if IS_ENABLED(COMPILER_SSE)
/* Enable sse instructions. */
mov %cr4, %eax
orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index 3d7952f..ba43164 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -16,6 +16,7 @@
#include <compiler.h>
#include <string.h>
#include <rmodule.h>
+#include <cpu/x86/sse.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/cache.h>
#include <console/console.h>
@@ -369,7 +370,7 @@
fxsave_size = 0;
fxsave_area = NULL;
- if (IS_ENABLED(CONFIG_SSE)) {
+ if (IS_ENABLED(COMPILER_SSE)) {
fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks;
/* FXSAVE area below all the stacks stack. */
fxsave_area = params->stack_top;
diff --git a/src/include/cpu/x86/sse.h b/src/include/cpu/x86/sse.h
new file mode 100644
index 0000000..9b6537c
--- /dev/null
+++ b/src/include/cpu/x86/sse.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef CPU_X86_SSE
+#define CPU_X86_SSE
+
+#if ((IS_ENABLED(__SSE__) || IS_ENABLED(__SSE2__) || \
+ IS_ENABLED(__SSE3__) || IS_ENABLED(__SSE4_1__) || \
+ IS_ENABLED(__SSE4_2__)) || \
+ (IS_ENABLED(_M_IX86_FP) && _M_IX86_FP == 1))
+#define COMPILER_SSE 1
+#endif
+
+#if ((IS_ENABLED(__SSE2__) || IS_ENABLED(__SSE3__) || \
+ IS_ENABLED(__SSE4_1__) || IS_ENABLED(__SSE4_2__)) || \
+ (IS_ENABLED(_M_IX86_FP) && _M_IX86_FP == 2))
+#define COMPILER_SSE2 1
+#endif
+
+#if (IS_ENABLED(__SSE3__) || IS_ENABLED(__SSE4_1__) || \
+ IS_ENABLED(__SSE4_2__))
+#define COMPILER_SSE3 1
+#endif
+
+#if (IS_ENABLED(__SSE4_1__) || IS_ENABLED(__SSE4_2__))
+#define COMPILER_SSE4_1 1
+#endif
+
+#if IS_ENABLED(__SSE4_2__)
+#define COMPILER_SSE4_2 1
+#endif
+
+#if IS_ENABLED(__AVX__)
+#define COMPILER_AVX 1
+#endif
+
+#if IS_ENABLED(__AVX2__)
+#define COMPILER_AVX2 1
+#endif
+
+#endif /* CPU_X86_SSE */
diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index 2b2c344..aace12b 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -1,3 +1,5 @@
+
+#include <cpu/x86/sse.h>
#include <stdint.h>
#include <lib.h> /* Prototypes */
#include <console/console.h>
@@ -6,7 +8,7 @@
{
// Assembler in lib/ is very ugly. But we properly guarded
// it so let's obey this one for now
-#if IS_ENABLED(CONFIG_SSE2)
+#if IS_ENABLED(COMPILER_SSE2)
asm volatile(
"movnti %1, (%0)"
: /* outputs */
@@ -31,7 +33,7 @@
static void phys_memory_barrier(void)
{
-#if IS_ENABLED(CONFIG_SSE2)
+#if IS_ENABLED(COMPILER_SSE2)
// Needed for movnti
asm volatile (
"sfence"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I787ed37d34125ea9f8919d67f3240fdee6c689ec
Gerrit-Change-Number: 20636
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
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