<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20636">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">x86/sse: Use compiler defined macros instead of Kconfig option<br><br>Compilers define a set of macros in case SSE has been enabled using the<br>-msse switch or by setting an architecture that supports SSE.<br><br>Define and use marcos to detect SSE enabled compilers.<br>In the next step we can get rid of CONFIG_SSE and CONFIG_SSE2.<br><br>Change-Id: I787ed37d34125ea9f8919d67f3240fdee6c689ec<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/arch/x86/assembly_entry.S<br>M src/arch/x86/bootblock_crt0.S<br>M src/arch/x86/bootblock_romcc.S<br>M src/cpu/x86/sipi_vector.S<br>M src/cpu/x86/smm/smm_module_loader.c<br>A src/include/cpu/x86/sse.h<br>M src/lib/ramtest.c<br>7 files changed, 66 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/20636/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S<br>index 220cc6e..3ab66c0 100644<br>--- a/src/arch/x86/assembly_entry.S<br>+++ b/src/arch/x86/assembly_entry.S<br>@@ -13,7 +13,7 @@<br> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br> * GNU General Public License for more details.<br> */<br>-<br>+#include <cpu/x86/sse.h><br> #include <rules.h><br> <br> /*<br>@@ -81,7 +81,7 @@<br> #include <arch/x86/prologue.inc><br> #include <cpu/x86/32bit/entry32.inc><br> #include <cpu/x86/fpu_enable.inc><br>-#if IS_ENABLED(CONFIG_SSE)<br>+#if IS_ENABLED(COMPILER_SSE)<br> #include <cpu/x86/sse_enable.inc><br> #endif<br> <br>diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S<br>index 1b160f4..9d10661 100644<br>--- a/src/arch/x86/bootblock_crt0.S<br>+++ b/src/arch/x86/bootblock_crt0.S<br>@@ -21,6 +21,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <cpu/x86/sse.h><br> #include <cpu/x86/cr.h><br> <br> /*<br>@@ -66,12 +67,12 @@<br> movd %edx, %mm2<br> #endif<br> <br>-#if IS_ENABLED(CONFIG_SSE)<br>+#if IS_ENABLED(COMPILER_SSE)<br> enable_sse:<br> mov %cr4, %eax<br> or $CR4_OSFXSR, %ax<br> mov %eax, %cr4<br>-#endif /* IS_ENABLED(CONFIG_SSE) */<br>+#endif /* IS_ENABLED(COMPILER_SSE) */<br> <br> /* We're done. Now it's up to platform-specific code */<br> jmp bootblock_pre_c_entry<br>diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S<br>index 6c1723a..3991e4e 100644<br>--- a/src/arch/x86/bootblock_romcc.S<br>+++ b/src/arch/x86/bootblock_romcc.S<br>@@ -30,6 +30,7 @@<br> * of the includes.<br> */<br> <br>+#include <cpu/x86/sse.h><br> #include <arch/x86/prologue.inc><br> #include <cpu/x86/16bit/entry16.inc><br> #include <cpu/x86/16bit/reset16.inc><br>@@ -39,7 +40,7 @@<br> #include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE<br> #endif<br> <br>-#if IS_ENABLED(CONFIG_SSE)<br>+#if IS_ENABLED(COMPILER_SSE)<br> #include <cpu/x86/sse_enable.inc><br> #endif<br> <br>diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S<br>index e654915..d1615c9 100644<br>--- a/src/cpu/x86/sipi_vector.S<br>+++ b/src/cpu/x86/sipi_vector.S<br>@@ -13,7 +13,7 @@<br> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br> * GNU General Public License for more details.<br> */<br>-<br>+#include <cpu/x86/sse.h><br> #include <cpu/x86/cr.h><br> <br> /* The SIPI vector is responsible for initializing the APs in the sytem. It<br>@@ -185,7 +185,7 @@<br> and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax<br> mov %eax, %cr0<br> <br>-#if IS_ENABLED(CONFIG_SSE)<br>+#if IS_ENABLED(COMPILER_SSE)<br> /* Enable sse instructions. */<br> mov %cr4, %eax<br> orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax<br>diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c<br>index 3d7952f..ba43164 100644<br>--- a/src/cpu/x86/smm/smm_module_loader.c<br>+++ b/src/cpu/x86/smm/smm_module_loader.c<br>@@ -16,6 +16,7 @@<br> #include <compiler.h><br> #include <string.h><br> #include <rmodule.h><br>+#include <cpu/x86/sse.h><br> #include <cpu/x86/smm.h><br> #include <cpu/x86/cache.h><br> #include <console/console.h><br>@@ -369,7 +370,7 @@<br> <br> fxsave_size = 0;<br> fxsave_area = NULL;<br>- if (IS_ENABLED(CONFIG_SSE)) {<br>+ if (IS_ENABLED(COMPILER_SSE)) {<br> fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks;<br> /* FXSAVE area below all the stacks stack. */<br> fxsave_area = params->stack_top;<br>diff --git a/src/include/cpu/x86/sse.h b/src/include/cpu/x86/sse.h<br>new file mode 100644<br>index 0000000..9b6537c<br>--- /dev/null<br>+++ b/src/include/cpu/x86/sse.h<br>@@ -0,0 +1,51 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef CPU_X86_SSE<br>+#define CPU_X86_SSE<br>+<br>+#if ((IS_ENABLED(__SSE__) || IS_ENABLED(__SSE2__) || \<br>+ IS_ENABLED(__SSE3__) || IS_ENABLED(__SSE4_1__) || \<br>+ IS_ENABLED(__SSE4_2__)) || \<br>+ (IS_ENABLED(_M_IX86_FP) && _M_IX86_FP == 1))<br>+#define COMPILER_SSE 1<br>+#endif<br>+<br>+#if ((IS_ENABLED(__SSE2__) || IS_ENABLED(__SSE3__) || \<br>+ IS_ENABLED(__SSE4_1__) || IS_ENABLED(__SSE4_2__)) || \<br>+ (IS_ENABLED(_M_IX86_FP) && _M_IX86_FP == 2))<br>+#define COMPILER_SSE2 1<br>+#endif<br>+<br>+#if (IS_ENABLED(__SSE3__) || IS_ENABLED(__SSE4_1__) || \<br>+ IS_ENABLED(__SSE4_2__))<br>+#define COMPILER_SSE3 1<br>+#endif<br>+<br>+#if (IS_ENABLED(__SSE4_1__) || IS_ENABLED(__SSE4_2__))<br>+#define COMPILER_SSE4_1 1<br>+#endif<br>+<br>+#if IS_ENABLED(__SSE4_2__)<br>+#define COMPILER_SSE4_2 1<br>+#endif<br>+<br>+#if IS_ENABLED(__AVX__)<br>+#define COMPILER_AVX 1<br>+#endif<br>+<br>+#if IS_ENABLED(__AVX2__)<br>+#define COMPILER_AVX2 1<br>+#endif<br>+<br>+#endif /* CPU_X86_SSE */<br>diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c<br>index 2b2c344..aace12b 100644<br>--- a/src/lib/ramtest.c<br>+++ b/src/lib/ramtest.c<br>@@ -1,3 +1,5 @@<br>+<br>+#include <cpu/x86/sse.h><br> #include <stdint.h><br> #include <lib.h> /* Prototypes */<br> #include <console/console.h><br>@@ -6,7 +8,7 @@<br> {<br> // Assembler in lib/ is very ugly. But we properly guarded<br> // it so let's obey this one for now<br>-#if IS_ENABLED(CONFIG_SSE2)<br>+#if IS_ENABLED(COMPILER_SSE2)<br> asm volatile(<br> "movnti %1, (%0)"<br> : /* outputs */<br>@@ -31,7 +33,7 @@<br> <br> static void phys_memory_barrier(void)<br> {<br>-#if IS_ENABLED(CONFIG_SSE2)<br>+#if IS_ENABLED(COMPILER_SSE2)<br> // Needed for movnti<br> asm volatile (<br> "sfence"<br></pre><p>To view, visit <a href="https://review.coreboot.org/20636">change 20636</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20636"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I787ed37d34125ea9f8919d67f3240fdee6c689ec </div>
<div style="display:none"> Gerrit-Change-Number: 20636 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>