[coreboot-gerrit] Change in coreboot[master]: 440BX Modernization project, part 1.

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/20629


Change subject: 440BX Modernization project, part 1.
......................................................................

440BX Modernization project, part 1.

- Implements get_top_of_ram() as first step towards
  cbmem in romstage.
- Moves NB macro into northbridge.h to make it more
  widely available.
- Merges 4 RAM init routines into one.

Signed-off-by: Keith Hui <buurin at gmail.com>

Change-Id: I2a5baf11dd557f7a3fc2cbe3f7816fbd16f94588
---
M src/northbridge/intel/i440bx/i440bx.h
M src/northbridge/intel/i440bx/northbridge.h
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i440bx/raminit.h
4 files changed, 34 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20629/1

diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h
index 4724719..6e93e83 100644
--- a/src/northbridge/intel/i440bx/i440bx.h
+++ b/src/northbridge/intel/i440bx/i440bx.h
@@ -86,4 +86,6 @@
 #define DRTC    0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
 #define BUFFC   0xf0 /* Buffer Control Register (0x0000). */
 
+#define NB PCI_DEV(0, 0, 0)
+
 #endif /* NORTHBRIDGE_INTEL_I440BX_I440BX_H */
diff --git a/src/northbridge/intel/i440bx/northbridge.h b/src/northbridge/intel/i440bx/northbridge.h
index 5b721b5..65dd4ac 100644
--- a/src/northbridge/intel/i440bx/northbridge.h
+++ b/src/northbridge/intel/i440bx/northbridge.h
@@ -18,5 +18,6 @@
 #define NORTHBRIDGE_INTEL_440BX_H
 
 extern unsigned int i440bx_scan_root_bus(device_t root, unsigned int max);
+extern unsigned long get_top_of_ram(void);
 
 #endif				/* NORTHBRIDGE_INTEL_440BX_H */
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 86e9595..d18c15d 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2008 Uwe Hermann <uwe at hermann-uwe.de>
- * Copyright (C) 2010 Keith Hui <buurin at gmail.com>
+ * Copyright (C) 2010,2017 Keith Hui <buurin at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,14 +22,15 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
+#include <cbmem.h>
+#include <timestamp.h>
 #include "i440bx.h"
 #include "raminit.h"
+#include "northbridge.h"
 
 /*-----------------------------------------------------------------------------
 Macros and definitions.
 -----------------------------------------------------------------------------*/
-
-#define NB PCI_DEV(0, 0, 0)
 
 /* Debugging macros. */
 #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
@@ -586,9 +587,9 @@
 	pci_write_config8(NB, MBFS + 2, mbfs2);
 }
 
-/*-----------------------------------------------------------------------------
-DIMM-independent configuration functions.
------------------------------------------------------------------------------*/
+/*
+ * DIMM-independent configuration functions.
+ */
 
 static void spd_enable_refresh(void)
 {
@@ -609,9 +610,9 @@
 	pci_write_config8(NB, DRAMC, reg);
 }
 
-/*-----------------------------------------------------------------------------
-Public interface.
------------------------------------------------------------------------------*/
+/*
+ * Public interface.
+ */
 
 void sdram_set_registers(void)
 {
@@ -981,3 +982,21 @@
 	PRINT_DEBUG("Northbridge following SDRAM init:\n");
 	DUMPNORTH();
 }
+
+void sdram_initialize(void)
+{
+	dump_spd_registers();
+	sdram_set_registers();
+	sdram_set_spd_registers();
+	sdram_enable();
+}
+
+/*
+ * CBMEM support functions.
+ */
+
+unsigned long get_top_of_ram(void)
+{
+	/* Top of RAM = DRB7 * 8MB */
+	return pci_read_config8(NB, DRB7) * 1048576 * 8;
+}
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index 609b591..c88510f 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -25,6 +25,9 @@
 void sdram_set_registers(void);
 void sdram_set_spd_registers(void);
 void sdram_enable(void);
+/* A merger of above functions. */
+void sdram_initialize(void);
+
 /* Debug */
 #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
 void dump_spd_registers(void);

-- 
To view, visit https://review.coreboot.org/20629
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2a5baf11dd557f7a3fc2cbe3f7816fbd16f94588
Gerrit-Change-Number: 20629
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin at gmail.com>
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