<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20629">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">440BX Modernization project, part 1.<br><br>- Implements get_top_of_ram() as first step towards<br> cbmem in romstage.<br>- Moves NB macro into northbridge.h to make it more<br> widely available.<br>- Merges 4 RAM init routines into one.<br><br>Signed-off-by: Keith Hui <buurin@gmail.com><br><br>Change-Id: I2a5baf11dd557f7a3fc2cbe3f7816fbd16f94588<br>---<br>M src/northbridge/intel/i440bx/i440bx.h<br>M src/northbridge/intel/i440bx/northbridge.h<br>M src/northbridge/intel/i440bx/raminit.c<br>M src/northbridge/intel/i440bx/raminit.h<br>4 files changed, 34 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20629/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h<br>index 4724719..6e93e83 100644<br>--- a/src/northbridge/intel/i440bx/i440bx.h<br>+++ b/src/northbridge/intel/i440bx/i440bx.h<br>@@ -86,4 +86,6 @@<br> #define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */<br> #define BUFFC 0xf0 /* Buffer Control Register (0x0000). */<br> <br>+#define NB PCI_DEV(0, 0, 0)<br>+<br> #endif /* NORTHBRIDGE_INTEL_I440BX_I440BX_H */<br>diff --git a/src/northbridge/intel/i440bx/northbridge.h b/src/northbridge/intel/i440bx/northbridge.h<br>index 5b721b5..65dd4ac 100644<br>--- a/src/northbridge/intel/i440bx/northbridge.h<br>+++ b/src/northbridge/intel/i440bx/northbridge.h<br>@@ -18,5 +18,6 @@<br> #define NORTHBRIDGE_INTEL_440BX_H<br> <br> extern unsigned int i440bx_scan_root_bus(device_t root, unsigned int max);<br>+extern unsigned long get_top_of_ram(void);<br> <br> #endif /* NORTHBRIDGE_INTEL_440BX_H */<br>diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c<br>index 86e9595..d18c15d 100644<br>--- a/src/northbridge/intel/i440bx/raminit.c<br>+++ b/src/northbridge/intel/i440bx/raminit.c<br>@@ -2,7 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de><br>- * Copyright (C) 2010 Keith Hui <buurin@gmail.com><br>+ * Copyright (C) 2010,2017 Keith Hui <buurin@gmail.com><br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -22,14 +22,15 @@<br> #include <arch/io.h><br> #include <device/pci_def.h><br> #include <console/console.h><br>+#include <cbmem.h><br>+#include <timestamp.h><br> #include "i440bx.h"<br> #include "raminit.h"<br>+#include "northbridge.h"<br> <br> /*-----------------------------------------------------------------------------<br> Macros and definitions.<br> -----------------------------------------------------------------------------*/<br>-<br>-#define NB PCI_DEV(0, 0, 0)<br> <br> /* Debugging macros. */<br> #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>@@ -586,9 +587,9 @@<br> pci_write_config8(NB, MBFS + 2, mbfs2);<br> }<br> <br>-/*-----------------------------------------------------------------------------<br>-DIMM-independent configuration functions.<br>------------------------------------------------------------------------------*/<br>+/*<br>+ * DIMM-independent configuration functions.<br>+ */<br> <br> static void spd_enable_refresh(void)<br> {<br>@@ -609,9 +610,9 @@<br> pci_write_config8(NB, DRAMC, reg);<br> }<br> <br>-/*-----------------------------------------------------------------------------<br>-Public interface.<br>------------------------------------------------------------------------------*/<br>+/*<br>+ * Public interface.<br>+ */<br> <br> void sdram_set_registers(void)<br> {<br>@@ -981,3 +982,21 @@<br> PRINT_DEBUG("Northbridge following SDRAM init:\n");<br> DUMPNORTH();<br> }<br>+<br>+void sdram_initialize(void)<br>+{<br>+ dump_spd_registers();<br>+ sdram_set_registers();<br>+ sdram_set_spd_registers();<br>+ sdram_enable();<br>+}<br>+<br>+/*<br>+ * CBMEM support functions.<br>+ */<br>+<br>+unsigned long get_top_of_ram(void)<br>+{<br>+ /* Top of RAM = DRB7 * 8MB */<br>+ return pci_read_config8(NB, DRB7) * 1048576 * 8;<br>+}<br>diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h<br>index 609b591..c88510f 100644<br>--- a/src/northbridge/intel/i440bx/raminit.h<br>+++ b/src/northbridge/intel/i440bx/raminit.h<br>@@ -25,6 +25,9 @@<br> void sdram_set_registers(void);<br> void sdram_set_spd_registers(void);<br> void sdram_enable(void);<br>+/* A merger of above functions. */<br>+void sdram_initialize(void);<br>+<br> /* Debug */<br> #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> void dump_spd_registers(void);<br></pre><p>To view, visit <a href="https://review.coreboot.org/20629">change 20629</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20629"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2a5baf11dd557f7a3fc2cbe3f7816fbd16f94588 </div>
<div style="display:none"> Gerrit-Change-Number: 20629 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>