[coreboot-gerrit] Change in coreboot[master]: intel/fsp: Rearrange post codes for FSP phase indication

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20541


Change subject: intel/fsp: Rearrange post codes for FSP phase indication
......................................................................

intel/fsp: Rearrange post codes for FSP phase indication

This patch will make it more consistent to debug FSP hang
and reset issues.

Bug=none
Branch=none
TEST=Build and Boot on eve

Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/include/console/post_codes.h
3 files changed, 21 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/20541/1

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 424a325..6d12047 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -360,7 +360,7 @@
 	post_code(POST_FSP_MEMORY_INIT);
 	timestamp_add_now(TS_FSP_MEMORY_INIT_START);
 	status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr());
-	post_code(POST_FSP_MEMORY_INIT);
+	post_code(POST_FSP_MEMORY_EXIT);
 	timestamp_add_now(TS_FSP_MEMORY_INIT_END);
 
 	fsp_debug_after_memory_init(status);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 9f0bf7c..bda88d1 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -49,7 +49,7 @@
 	post_code(POST_FSP_SILICON_INIT);
 	status = silicon_init(&upd);
 	timestamp_add_now(TS_FSP_SILICON_INIT_END);
-	post_code(POST_FSP_SILICON_INIT);
+	post_code(POST_FSP_SILICON_EXIT);
 
 	fsp_debug_after_silicon_init(status);
 
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 1368aa8..d10cf38 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -238,39 +238,53 @@
 #define POST_FSP_MEMORY_INIT			0x92
 
 /**
+ * \brief After calling FSP MemoryInit
+ *
+ * FSP binary returned from MemoryInit phase
+ */
+#define POST_FSP_MEMORY_EXIT			0x93
+
+/**
  * \brief Before calling FSP SiliconInit
  *
  * Going to call into FSP binary for SiliconInit phase
  */
-#define POST_FSP_SILICON_INIT			0x93
+#define POST_FSP_SILICON_INIT			0x94
+
+/**
+ * \brief After calling FSP SiliconInit
+ *
+ * FSP binary returned from SiliconInit phase
+ */
+#define POST_FSP_SILICON_EXIT			0x95
 
 /**
  * \brief Before calling FSP Notify before resource allocation
  *
  * Going to call into FSP binary for Notify phase
  */
-#define POST_FSP_NOTIFY_BEFORE_ENUMERATE	0x94
+#define POST_FSP_NOTIFY_BEFORE_ENUMERATE	0x96
 
 /**
  * \brief Before calling FSP Notify before finalize
  *
  * Going to call into FSP binary for Notify phase
  */
-#define POST_FSP_NOTIFY_BEFORE_FINALIZE		0x95
+#define POST_FSP_NOTIFY_BEFORE_FINALIZE		0x97
 
 /**
  * \brief Indicate OS _PTS entry
  *
  * Called from _PTS asl method
  */
-#define POST_OS_ENTER_PTS			0x96
+#define POST_OS_ENTER_PTS			0x98
 
 /**
  * \brief Indicate OS _WAK entry
  *
  * Called from within _WAK method
  */
-#define POST_OS_ENTER_WAKE			0x97
+#define POST_OS_ENTER_WAKE			0x99
 
 /**
  * \brief Entry into elf boot

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb
Gerrit-Change-Number: 20541
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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