[coreboot-gerrit] Change in coreboot[master]: fsp1_1: Don't look for FSP_SMBIOS_MEMORY_INFO_HOB in S3 flow

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20540


Change subject: fsp1_1: Don't look for FSP_SMBIOS_MEMORY_INFO_HOB in S3 flow
......................................................................

fsp1_1: Don't look for FSP_SMBIOS_MEMORY_INFO_HOB in S3 flow

FSP don't publish smbios_memory_info_guid during S3 resume
path. Hence its recommended to skip consuming this HOB in
S3 resume.

Bug=none
Branch=none
TEST=Build and boot Lars system with this patch.

Change-Id: I321751523b1ea3326ffc23f4d4c53d5362482674
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/drivers/intel/fsp1_1/romstage.c
1 file changed, 5 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/20540/1

diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index c2fc667..01f484e 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -101,6 +101,7 @@
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
+	bool s3wake;
 	struct region_device rdev;
 	struct pei_data *pei_data;
 
@@ -110,9 +111,10 @@
 
 	pei_data = params->pei_data;
 	pei_data->boot_mode = params->power_state->prev_sleep_state;
+	s3wake = params->power_state->prev_sleep_state == ACPI_S3;
 
 #if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
-	if (params->power_state->prev_sleep_state != ACPI_S3)
+	if (!s3wake)
 		boot_count_increment();
 #endif
 
@@ -168,7 +170,8 @@
 	}
 
 	/* Save DIMM information */
-	mainboard_save_dimm_info(params);
+	if (!s3wake)
+		mainboard_save_dimm_info(params);
 
 	/* Create romstage handof information */
 	if (romstage_handoff_init(

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I321751523b1ea3326ffc23f4d4c53d5362482674
Gerrit-Change-Number: 20540
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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