[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add postcar stage support

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20534


Change subject: soc/intel/cannonlake: Add postcar stage support
......................................................................

soc/intel/cannonlake: Add postcar stage support

Initilize postcar frame once finish FSP memoryinit

Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/drivers/intel/fsp2_0/Makefile.inc
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/romstage/romstage.c
4 files changed, 39 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/20534/1

diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index cdf6146..d5709ad 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -43,6 +43,7 @@
 postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
 postcar-$(CONFIG_FSP_CAR) += util.c
 postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
+postcar-y += hand_off_block.c
 
 CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
 
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 2c60309..54abba0 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -23,6 +23,8 @@
 	select HAVE_INTEL_FIRMWARE
 	select INTEL_CAR_NEM_ENHANCED
 	select PLATFORM_USES_FSP2_0
+	select POSTCAR_CONSOLE
+	select POSTCAR_STAGE
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index b0fe57f..a5cb463 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -20,6 +20,9 @@
 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
 ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
 
+postcar-y += memmap.c
+postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake
 
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 5a860a2..8144b3a 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -14,6 +14,10 @@
  */
 
 #include <arch/io.h>
+#include <arch/symbols.h>
+#include <assert.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/util.h>
@@ -22,9 +26,17 @@
 #include <soc/romstage.h>
 #include <timestamp.h>
 
+/*
+ * Romstage needs some stack for decompressing ramstage images, since the lzma
+ * lib keeps its state on the stack during romstage.
+ */
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
 asmlinkage void car_stage_entry(void)
 {
 	bool s3wake;
+	struct postcar_frame pcf;
+	uintptr_t top_of_ram;
 	struct chipset_power_state *ps;
 
 	console_init();
@@ -36,8 +48,29 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 	s3wake = ps->prev_sleep_state == ACPI_S3;
 	fsp_memory_init(s3wake);
+	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+		die("Unable to initialize postcar frame.\n");
+
+	/*
+	 * We need to make sure ramstage will be run cached. At this
+	 * point exact location of ramstage in cbmem is not known.
+	 * Instruct postcar to cache 16 megs under cbmem top which is
+	 * a safe bet to cover ramstage.
+	 */
+	top_of_ram = (uintptr_t) cbmem_top();
+	printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+	top_of_ram -= 16*MiB;
+	postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+	/* Cache the ROM as WP just below 4GiB. */
+	postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
+				CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+	run_postcar_phase(&pcf);
 }
+
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
+	mainboard_memory_init_params(mupd);
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Gerrit-Change-Number: 20534
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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