<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20534">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add postcar stage support<br><br>Initilize postcar frame once finish FSP memoryinit<br><br>Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/drivers/intel/fsp2_0/Makefile.inc<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>4 files changed, 39 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/20534/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc<br>index cdf6146..d5709ad 100644<br>--- a/src/drivers/intel/fsp2_0/Makefile.inc<br>+++ b/src/drivers/intel/fsp2_0/Makefile.inc<br>@@ -43,6 +43,7 @@<br> postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c<br> postcar-$(CONFIG_FSP_CAR) += util.c<br> postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c<br>+postcar-y += hand_off_block.c<br> <br> CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include<br> <br>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 2c60309..54abba0 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -23,6 +23,8 @@<br> select HAVE_INTEL_FIRMWARE<br> select INTEL_CAR_NEM_ENHANCED<br> select PLATFORM_USES_FSP2_0<br>+ select POSTCAR_CONSOLE<br>+ select POSTCAR_STAGE<br> select SOC_INTEL_COMMON<br> select SOC_INTEL_COMMON_BLOCK_SA<br> select SOC_INTEL_COMMON_BLOCK<br>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index b0fe57f..a5cb463 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -20,6 +20,9 @@<br> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br> ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c<br> <br>+postcar-y += memmap.c<br>+postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c<br>+<br> CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20<br> CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake<br> <br>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c<br>index 5a860a2..8144b3a 100644<br>--- a/src/soc/intel/cannonlake/romstage/romstage.c<br>+++ b/src/soc/intel/cannonlake/romstage/romstage.c<br>@@ -14,6 +14,10 @@<br> */<br> <br> #include <arch/io.h><br>+#include <arch/symbols.h><br>+#include <assert.h><br>+#include <cpu/x86/mtrr.h><br>+#include <cpu/x86/msr.h><br> #include <cbmem.h><br> #include <console/console.h><br> #include <fsp/util.h><br>@@ -22,9 +26,17 @@<br> #include <soc/romstage.h><br> #include <timestamp.h><br> <br>+/*<br>+ * Romstage needs some stack for decompressing ramstage images, since the lzma<br>+ * lib keeps its state on the stack during romstage.<br>+ */<br>+#define ROMSTAGE_RAM_STACK_SIZE 0x5000<br>+<br> asmlinkage void car_stage_entry(void)<br> {<br> bool s3wake;<br>+ struct postcar_frame pcf;<br>+ uintptr_t top_of_ram;<br> struct chipset_power_state *ps;<br> <br> console_init();<br>@@ -36,8 +48,29 @@<br> timestamp_add_now(TS_START_ROMSTAGE);<br> s3wake = ps->prev_sleep_state == ACPI_S3;<br> fsp_memory_init(s3wake);<br>+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))<br>+ die("Unable to initialize postcar frame.\n");<br>+<br>+ /*<br>+ * We need to make sure ramstage will be run cached. At this<br>+ * point exact location of ramstage in cbmem is not known.<br>+ * Instruct postcar to cache 16 megs under cbmem top which is<br>+ * a safe bet to cover ramstage.<br>+ */<br>+ top_of_ram = (uintptr_t) cbmem_top();<br>+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);<br>+ top_of_ram -= 16*MiB;<br>+ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);<br>+<br>+ /* Cache the ROM as WP just below 4GiB. */<br>+ postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,<br>+ CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);<br>+<br>+ run_postcar_phase(&pcf);<br> }<br>+<br> <br> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)<br> {<br>+ mainboard_memory_init_params(mupd);<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/20534">change 20534</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20534"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 </div>
<div style="display:none"> Gerrit-Change-Number: 20534 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>