[coreboot-gerrit] Change in coreboot[master]: intel/cannonlake_rvp: Split RVP boards and SPD
Lijian Zhao (Code Review)
gerrit at coreboot.org
Sun Jul 9 03:38:00 CEST 2017
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20503
Change subject: intel/cannonlake_rvp: Split RVP boards and SPD
......................................................................
intel/cannonlake_rvp: Split RVP boards and SPD
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/Kconfig
M src/mainboard/intel/cannonlake_rvp/Kconfig.name
M src/mainboard/intel/cannonlake_rvp/Makefile.inc
M src/mainboard/intel/cannonlake_rvp/romstage.c
A src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc
A src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex
A src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex
A src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex
A src/mainboard/intel/cannonlake_rvp/spd/spd.h
A src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
A src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
A src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
12 files changed, 339 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/20503/1
diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig
index 54cd3f6..c59abcf 100644
--- a/src/mainboard/intel/cannonlake_rvp/Kconfig
+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig
@@ -1,13 +1,19 @@
-if BOARD_INTEL_CANNONLAKE_RVP
+if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select SOC_INTEL_CANNONLAKE
+ select GENERIC_SPD_BIN
config MAINBOARD_DIR
string
default "intel/cannonlake_rvp"
+
+config VARIANT_DIR
+ string
+ default "cnl_u" if BOARD_INTEL_CANNONLAKE_RVPU
+ default "cnl_y" if BOARD_INTEL_CANNONLAKE_RVPY
config MAINBOARD_PART_NUMBER
string
@@ -16,6 +22,10 @@
config MAINBOARD_VENDOR
string
default "Intel"
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
config IFD_BIN_PATH
string
@@ -32,4 +42,8 @@
depends on HAVE_EC_BIN
default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin"
+config DIMM_SPD_SIZE
+ int
+ default 512
+
endif
diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig.name b/src/mainboard/intel/cannonlake_rvp/Kconfig.name
index 4935603..1102e39 100644
--- a/src/mainboard/intel/cannonlake_rvp/Kconfig.name
+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig.name
@@ -1,2 +1,4 @@
-config BOARD_INTEL_CANNONLAKE_RVP
- bool "Cannonlake DDR4 RVP"
+config BOARD_INTEL_CANNONLAKE_RVPU
+ bool "Cannonlake U DDR4 RVP"
+config BOARD_INTEL_CANNONLAKE_RVPY
+ bool "Cannonlake Y LPDDR4 RVP"
diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc
index 75c34dd..dd8303f 100644
--- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc
+++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc
@@ -1 +1,20 @@
-#Nothing here yet
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2017 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c
index 1f58c2c..632bcb6 100644
--- a/src/mainboard/intel/cannonlake_rvp/romstage.c
+++ b/src/mainboard/intel/cannonlake_rvp/romstage.c
@@ -14,4 +14,48 @@
* GNU General Public License for more details.
*/
-//Nothing here yet, but file needed for build.
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include "spd/spd.h"
+#include <string.h>
+#include <spd_bin.h>
+
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ mem_cfg = &mupd->FspmConfig;
+ u8 spd_index = 0;
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {
+ mem_cfg->DqPinsInterleaved = 1;
+ mem_cfg->CaVrefConfig = 2; /* DDR4 */
+ spd_index = 1;
+ }
+ else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */
+ mem_cfg->DqPinsInterleaved = 0;
+ mem_cfg->CaVrefConfig = 0; /* LPDDR4 */
+ spd_index = 2;
+ }
+
+ printk(BIOS_DEBUG,"SPD INDEX =0x%u\n",spd_index);
+
+ struct region_device spd_rdev;
+
+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+ die("spd.bin not found\n");
+
+ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
+ /* Memory leak is ok since we have memory mapped boot media */
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
+ mem_cfg->RefClk = 0; /* Auto Select CLK freq */
+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+}
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc
new file mode 100644
index 0000000..656d5b9
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = empty # 0b000
+SPD_SOURCES += samsung_ddr4_4GB # 1b001 Dual Channel 4GB
+SPD_SOURCES += samsung_lpddr4_8GB # 2b001 Dual Channel 8GB
+SPD_SOURCES += empty # 3b011
+SPD_SOURCES += empty # 4b100
+SPD_SOURCES += empty # 5b101
+SPD_SOURCES += empty # 6b110
+SPD_SOURCES += empty # 7b111
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex
new file mode 100644
index 0000000..67b46cd
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex
new file mode 100644
index 0000000..49db237
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08
+00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
+16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20
+0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31
+34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE
+00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00
+01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex
new file mode 100644
index 0000000..d298629
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex
@@ -0,0 +1,32 @@
+23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00
+48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h
new file mode 100644
index 0000000..f2b6f2a
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define RCOMP_TARGET_PARAMS 0x5
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr);
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+#endif
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
new file mode 100644
index 0000000..ff6b09f
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <stdint.h>
+#include <string.h>
+#include "spd.h"
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+ /* DQ byte map */
+ const u8 dq_map_u[2][12] = {
+ { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } };
+
+ const u8 dq_map_y[2][12] = {
+ { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } };
+
+ if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {
+ memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u));
+ }
+ else {
+ memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y));
+ }
+}
+
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map_u[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+
+ const u8 dqs_map_y[2][8] = {
+ { 2, 0, 3, 1, 6, 5, 7, 4 },
+ { 3, 1, 2, 0, 4, 5, 6, 7 } };
+
+ if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {
+ memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
+ }
+ else {
+ memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
+ }
+}
+
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 100, 100, 100 };
+ memcpy(rcomp_ptr, RcompResistor,
+ sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = {
+ 100, 33, 32, 33, 28 };
+
+ static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = {
+ 80, 40, 40, 40, 30 };
+
+ if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {
+ memcpy(rcomp_strength_ptr, RcompTarget_U, sizeof(RcompTarget_U));
+ }
+ else {
+ memcpy(rcomp_strength_ptr, RcompTarget_Y, sizeof(RcompTarget_Y));
+ }
+}
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
new file mode 100644
index 0000000..c7001a4
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -0,0 +1,9 @@
+chip soc/intel/cannonlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ end
+end
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
new file mode 100644
index 0000000..c7001a4
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -0,0 +1,9 @@
+chip soc/intel/cannonlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ end
+end
--
To view, visit https://review.coreboot.org/20503
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Gerrit-Change-Number: 20503
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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