<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20503">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/cannonlake_rvp: Split RVP boards and SPD<br><br>Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.<br>Implement SPD entry to FSPM for both platforms, seperated platform<br>specific DQ/DQS/Rcomp input to FSPM as well.<br><br>Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/Kconfig<br>M src/mainboard/intel/cannonlake_rvp/Kconfig.name<br>M src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>M src/mainboard/intel/cannonlake_rvp/romstage.c<br>A src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc<br>A src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex<br>A src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex<br>A src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex<br>A src/mainboard/intel/cannonlake_rvp/spd/spd.h<br>A src/mainboard/intel/cannonlake_rvp/spd/spd_util.c<br>A src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>A src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>12 files changed, 339 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/20503/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig<br>index 54cd3f6..c59abcf 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/Kconfig<br>+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig<br>@@ -1,13 +1,19 @@<br>-if BOARD_INTEL_CANNONLAKE_RVP<br>+if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY<br> <br> config BOARD_SPECIFIC_OPTIONS<br> def_bool y<br> select BOARD_ROMSIZE_KB_16384<br> select SOC_INTEL_CANNONLAKE<br>+ select GENERIC_SPD_BIN<br> <br> config MAINBOARD_DIR<br> string<br> default "intel/cannonlake_rvp"<br>+<br>+config VARIANT_DIR<br>+ string<br>+ default "cnl_u" if BOARD_INTEL_CANNONLAKE_RVPU<br>+ default "cnl_y" if BOARD_INTEL_CANNONLAKE_RVPY<br> <br> config MAINBOARD_PART_NUMBER<br> string<br>@@ -16,6 +22,10 @@<br> config MAINBOARD_VENDOR<br> string<br> default "Intel"<br>+<br>+config DEVICETREE<br>+ string<br>+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"<br> <br> config IFD_BIN_PATH<br> string<br>@@ -32,4 +42,8 @@<br> depends on HAVE_EC_BIN<br> default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin"<br> <br>+config DIMM_SPD_SIZE<br>+ int<br>+ default 512<br>+<br> endif<br>diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig.name b/src/mainboard/intel/cannonlake_rvp/Kconfig.name<br>index 4935603..1102e39 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/Kconfig.name<br>+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig.name<br>@@ -1,2 +1,4 @@<br>-config BOARD_INTEL_CANNONLAKE_RVP<br>- bool "Cannonlake DDR4 RVP"<br>+config BOARD_INTEL_CANNONLAKE_RVPU<br>+ bool "Cannonlake U DDR4 RVP"<br>+config BOARD_INTEL_CANNONLAKE_RVPY<br>+ bool "Cannonlake Y LPDDR4 RVP"<br>diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>index 75c34dd..dd8303f 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>+++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>@@ -1 +1,20 @@<br>-#Nothing here yet<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2013 Google Inc.<br>+## Copyright (C) 2017 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+subdirs-y += spd<br>+<br>+subdirs-y += variants/$(VARIANT_DIR)<br>+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include<br>diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c<br>index 1f58c2c..632bcb6 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/romstage.c<br>+++ b/src/mainboard/intel/cannonlake_rvp/romstage.c<br>@@ -14,4 +14,48 @@<br> * GNU General Public License for more details.<br> */<br> <br>-//Nothing here yet, but file needed for build.<br>+#include <arch/byteorder.h><br>+#include <cbfs.h><br>+#include <console/console.h><br>+#include <fsp/api.h><br>+#include <soc/romstage.h><br>+#include "spd/spd.h"<br>+#include <string.h><br>+#include <spd_bin.h><br>+<br>+<br>+void mainboard_memory_init_params(FSPM_UPD *mupd)<br>+{<br>+ FSP_M_CONFIG *mem_cfg;<br>+ mem_cfg = &mupd->FspmConfig;<br>+ u8 spd_index = 0;<br>+<br>+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);<br>+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);<br>+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);<br>+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);<br>+<br>+ if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {<br>+ mem_cfg->DqPinsInterleaved = 1;<br>+ mem_cfg->CaVrefConfig = 2; /* DDR4 */<br>+ spd_index = 1;<br>+ }<br>+ else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */<br>+ mem_cfg->DqPinsInterleaved = 0;<br>+ mem_cfg->CaVrefConfig = 0; /* LPDDR4 */<br>+ spd_index = 2;<br>+ }<br>+<br>+ printk(BIOS_DEBUG,"SPD INDEX =0x%u\n",spd_index);<br>+<br>+ struct region_device spd_rdev;<br>+<br>+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)<br>+ die("spd.bin not found\n");<br>+<br>+ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);<br>+ /* Memory leak is ok since we have memory mapped boot media */<br>+ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);<br>+ mem_cfg->RefClk = 0; /* Auto Select CLK freq */<br>+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;<br>+}<br>diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc<br>new file mode 100644<br>index 0000000..656d5b9<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc<br>@@ -0,0 +1,28 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2014 Google Inc.<br>+## Copyright (C) 2015 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+romstage-y += spd_util.c<br>+<br>+SPD_BIN = $(obj)/spd.bin<br>+<br>+SPD_SOURCES = empty # 0b000<br>+SPD_SOURCES += samsung_ddr4_4GB # 1b001 Dual Channel 4GB<br>+SPD_SOURCES += samsung_lpddr4_8GB # 2b001 Dual Channel 8GB<br>+SPD_SOURCES += empty # 3b011<br>+SPD_SOURCES += empty # 4b100<br>+SPD_SOURCES += empty # 5b101<br>+SPD_SOURCES += empty # 6b110<br>+SPD_SOURCES += empty # 7b111<br>diff --git a/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex<br>new file mode 100644<br>index 0000000..67b46cd<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex<br>@@ -0,0 +1,32 @@<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex<br>new file mode 100644<br>index 0000000..49db237<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex<br>@@ -0,0 +1,32 @@<br>+23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00<br>+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08<br>+00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04<br>+16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20<br>+0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31<br>+34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE<br>+00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00<br>+01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex<br>new file mode 100644<br>index 0000000..d298629<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex<br>@@ -0,0 +1,32 @@<br>+23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00<br>+48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0<br>+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20<br>+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h<br>new file mode 100644<br>index 0000000..f2b6f2a<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd.h<br>@@ -0,0 +1,26 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef MAINBOARD_SPD_H<br>+#define MAINBOARD_SPD_H<br>+<br>+#define RCOMP_TARGET_PARAMS 0x5<br>+<br>+void mainboard_fill_dq_map_data(void *dq_map_ptr);<br>+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);<br>+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);<br>+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);<br>+#endif<br>diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c<br>new file mode 100644<br>index 0000000..ff6b09f<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c<br>@@ -0,0 +1,87 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+#include <arch/byteorder.h><br>+#include <cbfs.h><br>+#include <console/console.h><br>+#include <stdint.h><br>+#include <string.h><br>+#include "spd.h"<br>+<br>+void mainboard_fill_dq_map_data(void *dq_map_ptr)<br>+{<br>+ /* DQ byte map */<br>+ const u8 dq_map_u[2][12] = {<br>+ { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,<br>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },<br>+ { 0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00,<br>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } };<br>+<br>+ const u8 dq_map_y[2][12] = {<br>+ { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,<br>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },<br>+ { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,<br>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } };<br>+<br>+ if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {<br>+ memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u));<br>+ }<br>+ else {<br>+ memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y));<br>+ }<br>+}<br>+<br>+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)<br>+{<br>+ /* DQS CPU<>DRAM map */<br>+ const u8 dqs_map_u[2][8] = {<br>+ { 0, 1, 3, 2, 4, 5, 6, 7 },<br>+ { 1, 0, 4, 5, 2, 3, 6, 7 } };<br>+<br>+ const u8 dqs_map_y[2][8] = {<br>+ { 2, 0, 3, 1, 6, 5, 7, 4 },<br>+ { 3, 1, 2, 0, 4, 5, 6, 7 } };<br>+<br>+ if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {<br>+ memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));<br>+ }<br>+ else {<br>+ memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));<br>+ } <br>+}<br>+<br>+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)<br>+{<br>+ /* Rcomp resistor */<br>+ const u16 RcompResistor[3] = { 100, 100, 100 };<br>+ memcpy(rcomp_ptr, RcompResistor,<br>+ sizeof(RcompResistor));<br>+}<br>+<br>+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)<br>+{<br>+ /* Rcomp target */<br>+ static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = {<br>+ 100, 33, 32, 33, 28 };<br>+<br>+ static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = {<br>+ 80, 40, 40, 40, 30 };<br>+<br>+ if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {<br>+ memcpy(rcomp_strength_ptr, RcompTarget_U, sizeof(RcompTarget_U));<br>+ }<br>+ else {<br>+ memcpy(rcomp_strength_ptr, RcompTarget_Y, sizeof(RcompTarget_Y));<br>+ }<br>+}<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>new file mode 100644<br>index 0000000..c7001a4<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>@@ -0,0 +1,9 @@<br>+chip soc/intel/cannonlake<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+<br>+ device domain 0 on<br>+ end<br>+end<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>new file mode 100644<br>index 0000000..c7001a4<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>@@ -0,0 +1,9 @@<br>+chip soc/intel/cannonlake<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+<br>+ device domain 0 on<br>+ end<br>+end<br></pre><p>To view, visit <a href="https://review.coreboot.org/20503">change 20503</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20503"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 </div>
<div style="display:none"> Gerrit-Change-Number: 20503 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>