[coreboot-gerrit] Change in coreboot[master]: autoport: move spi_uvscc and spi_lvscc to devicetree.cb

[Iru Cai (Code Review)]

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/20486


Change subject: autoport: move spi_uvscc and spi_lvscc to devicetree.cb
......................................................................

autoport: move spi_uvscc and spi_lvscc to devicetree.cb

Change-Id: I36866cc793b3ddf9a78fed2e2840958d08327e7d
Signed-off-by: Iru Cai <mytbk920423 at gmail.com>
---
M util/autoport/bd82x6x.go
1 file changed, 2 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/20486/1

diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index 026ae51..0186564 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -179,10 +179,6 @@
 
 	/* SPI init */
 	MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h")
-	/* FIXME:XX Move this to runtime.  */
-	for _, addr := range []uint16{0x38c8, 0x38c4} {
-		MainboardInit += fmt.Sprintf("\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr])
-	}
 
 	FADT := ctx.InfoSource.GetACPI()["FACP"]
 
@@ -220,6 +216,8 @@
 			"p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
 			"c2_latency":                 FormatHexLE16(FADT[96:98]),
 			"docking_supported":          (FormatBool((FADT[113] & (1 << 1)) != 0)),
+			"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
+			"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4] &^ (1 << 23)),
 		},
 		PCISlots: []PCISlot{
 			PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I36866cc793b3ddf9a78fed2e2840958d08327e7d
Gerrit-Change-Number: 20486
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai <mytbk920423 at gmail.com>
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