[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/skylake: Add support in SKL for PMC common code
Shaunak Saha (Code Review)
gerrit at coreboot.org
Thu Jul 6 19:17:35 CEST 2017
Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/20219
Change subject: [WIP]soc/intel/skylake: Add support in SKL for PMC common code
......................................................................
[WIP]soc/intel/skylake: Add support in SKL for PMC common code
Change-Id: If7be9860bdd7d825bb7302168501129f09ca4741
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/include/soc/gpe.h
M src/soc/intel/skylake/include/soc/pm.h
D src/soc/intel/skylake/include/soc/pmc.h
M src/soc/intel/skylake/include/soc/smbus.h
M src/soc/intel/skylake/lpc.c
M src/soc/intel/skylake/pmc.c
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/skylake/reset.c
M src/soc/intel/skylake/romstage/power_state.c
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smi.c
M src/soc/intel/skylake/smihandler.c
16 files changed, 234 insertions(+), 585 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/20219/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 26f9021..b59f9c9 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -59,6 +59,7 @@
select SOC_INTEL_COMMON_BLOCK_I2C
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCIE
+ select SOC_INTEL_COMMON_BLOCK_PMC
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 780c4aa..750463c 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -22,6 +22,7 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
+#include <intelblocks/pmclib.h>
#include <intelblocks/smbus.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
@@ -31,7 +32,6 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#include <soc/pmc.h>
#include <soc/smbus.h>
#define PCR_DMI_LPCLGIR1 0x2730
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b4f6545..0231110 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -28,10 +28,10 @@
#include <soc/gpe.h>
#include <soc/irq.h>
#include <soc/pci_devs.h>
-#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
#include <soc/vr_config.h>
+#include <soc/pm.h>
#define SKYLAKE_I2C_DEV_MAX 6
diff --git a/src/soc/intel/skylake/include/soc/gpe.h b/src/soc/intel/skylake/include/soc/gpe.h
index 655cc11..d0962b8 100644
--- a/src/soc/intel/skylake/include/soc/gpe.h
+++ b/src/soc/intel/skylake/include/soc/gpe.h
@@ -130,4 +130,6 @@
#define GPE0_LAN_WAK 112
#define GPE0_WADT 114
+#define GPE_MAX GPE0_WADT
+
#endif /* _SOC_GPE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 15c291c..bf99734 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -19,7 +19,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
-#include <soc/pmc.h>
+#include <soc/smbus.h>
/* ACPI_BASE_ADDRESS / PMBASE */
@@ -135,6 +135,94 @@
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
+#define EN_BLOCK 3
+
+/* PCI Configuration Space (D31:F2): PMC */
+#define ABASE 0x40
+#define ACTL 0x44
+#define PWRM_EN (1 << 8)
+#define ACPI_EN (1 << 7)
+#define SCI_IRQ_SEL (7 << 0)
+#define SCIS_IRQ9 0
+#define SCIS_IRQ10 1
+#define SCIS_IRQ11 2
+#define SCIS_IRQ20 4
+#define SCIS_IRQ21 5
+#define SCIS_IRQ22 6
+#define SCIS_IRQ23 7
+#define PWRMBASE 0x48
+#define GEN_PMCON_A 0xa0
+#define DC_PP_DIS (1 << 30)
+#define DSX_PP_DIS (1 << 29)
+#define AG3_PP_EN (1 << 28)
+#define SX_PP_EN (1 << 27)
+#define DISB (1 << 23)
+#define MEM_SR (1 << 21)
+#define MS4V (1 << 18)
+#define GBL_RST_STS (1 << 16)
+#define ALLOW_ICLK_PLL_SD_INC0 (1 << 15)
+#define MPHY_CRICLK_GATE_OVER (1 << 14)
+#define ALLOW_OPI_PLL_SD_INC0 (1 << 13)
+#define ALLOW_SPXB_CG_INC0 (1 << 12)
+#define BIOS_PCI_EXP_EN (1 << 10)
+#define PWRBTN_LVL (1 << 9)
+#define ALLOW_L1LOW_C0 (1 << 7)
+#define ALLOW_L1LOW_OPI_ON (1 << 6)
+#define SMI_LOCK (1 << 4)
+#define GEN_PMCON_B 0xa4
+#define SLP_STR_POL_LOCK (1 << 18)
+#define ACPI_BASE_LOCK (1 << 17)
+#define SUS_PWR_FLR (1 << 14)
+#define WOL_EN_OVRD (1 << 13)
+#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
+#define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10)
+#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)
+#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)
+#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)
+#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)
+#define HOST_RST_STS (1 << 9)
+#define S4MAW_MASK (0x3 << 4)
+#define S4MAW_1S (1 << 4)
+#define S4MAW_2S (2 << 4)
+#define S4MAW_3S (3 << 4)
+#define S4MAW_4S (0 << 4)
+#define S4ASE (1 << 3)
+#define RTC_BATTERY_DEAD (1 << 2)
+#define PWR_FLR (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
+#define ETR 0xac
+# define CF9_LOCK (1 << 31)
+# define CF9_GLB_RST (1 << 20)
+
+/* Memory mapped IO registers in PMC */
+#define S3_PWRGATE_POL 0x28
+#define S3DC_GATE_SUS (1 << 1)
+#define S3AC_GATE_SUS (1 << 0)
+#define S4_PWRGATE_POL 0x2c
+#define S4DC_GATE_SUS (1 << 1)
+#define S4AC_GATE_SUS (1 << 0)
+#define S5_PWRGATE_POL 0x30
+#define S5DC_GATE_SUS (1 << 15)
+#define S5AC_GATE_SUS (1 << 14)
+#define DSX_CFG 0x34
+#define DSX_CFG_MASK 0x7
+#define DSX_EN_WAKE_PIN (1 << 2)
+#define DSX_EN_AC_PRESENT_PIN (1 << 1)
+#define DSX_EN_LAN_WAKE_PIN (1 << 0)
+#define PMSYNC_TPR_CFG 0xc4
+#define PMSYNC_LOCK (1 << 31)
+#define GPIO_GPE_CFG 0x120
+#define GPE0_DWX_MASK 0xf
+#define GPE0_DW0_SHIFT 0
+#define GPE0_DW1_SHIFT 4
+#define GPE0_DW2_SHIFT 8
+#define GBLRST_CAUSE0 0x124
+#define GBLRST_CAUSE1 0x128
+#define CIR31C 0x31c
+#define XTALSDQDIS (1 << 22)
+#define PRSTS 0x10
+
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;
@@ -149,46 +237,45 @@
uint32_t prev_sleep_state;
} __attribute__ ((packed));
-struct chipset_power_state *fill_power_state(void);
-
-/* PM1_CNT */
-void enable_pm1_control(uint32_t mask);
-void disable_pm1_control(uint32_t mask);
-
-/* PM1 */
-uint16_t clear_pm1_status(void);
-void enable_pm1(uint16_t events);
-uint32_t clear_smi_status(void);
-
-/* SMI */
-void enable_smi(uint32_t mask);
-void disable_smi(uint32_t mask);
/* TCO */
-uint32_t clear_tco_status(void);
void enable_tco_sci(void);
/* GPE0 */
uint32_t clear_gpe_status(void);
void clear_gpe_enable(void);
void enable_all_gpe(uint32_t set1, uint32_t set2, uint32_t set3, uint32_t set4);
-void disable_all_gpe(void);
-void enable_gpe(uint32_t mask);
-void disable_gpe(uint32_t mask);
/* Return the selected ACPI SCI IRQ */
int acpi_sci_irq(void);
/* Get base address PMC memory mapped registers. */
uint8_t *pmc_mmio_regs(void);
+uintptr_t soc_read_pmc_base(void);
+void soc_clear_status(uintptr_t pmc_bar);
/* Get base address of TCO I/O registers. */
uint16_t smbus_tco_regs(void);
+uint16_t soc_tco_base(void);
+uint32_t soc_reset_tco(void);
/* Set the DISB after DRAM init */
void pmc_set_disb(void);
/* Initialize GPEs */
-void pmc_gpe_init(void);
+uint8_t soc_get_devicetree_info(int8_t *dw0, int8_t *dw1, int8_t *dw2);
+
+int soc_fill_power_state(void);
+
+void chipset_prev_sleep_state(struct chipset_power_state *ps,
+ int *prev_sleep_state);
+
+
+const char * const *soc_gpe_sts_array(int *a);
+const char * const *soc_smi_sts_array(int *a);
+const char * const *soc_tco_sts_array(int *a);
+
+void global_reset_lock(void);
+void global_reset_enable(bool enable);
static inline int deep_s3_enabled(void)
{
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
deleted file mode 100644
index 4a80917..0000000
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_PMC_H_
-#define _SOC_PMC_H_
-
-/* PCI Configuration Space (D31:F2): PMC */
-#define ABASE 0x40
-#define ACTL 0x44
-#define PWRM_EN (1 << 8)
-#define ACPI_EN (1 << 7)
-#define SCI_IRQ_SEL (7 << 0)
-#define SCIS_IRQ9 0
-#define SCIS_IRQ10 1
-#define SCIS_IRQ11 2
-#define SCIS_IRQ20 4
-#define SCIS_IRQ21 5
-#define SCIS_IRQ22 6
-#define SCIS_IRQ23 7
-#define PWRMBASE 0x48
-#define GEN_PMCON_A 0xa0
-#define DC_PP_DIS (1 << 30)
-#define DSX_PP_DIS (1 << 29)
-#define AG3_PP_EN (1 << 28)
-#define SX_PP_EN (1 << 27)
-#define DISB (1 << 23)
-#define MEM_SR (1 << 21)
-#define MS4V (1 << 18)
-#define GBL_RST_STS (1 << 16)
-#define ALLOW_ICLK_PLL_SD_INC0 (1 << 15)
-#define MPHY_CRICLK_GATE_OVER (1 << 14)
-#define ALLOW_OPI_PLL_SD_INC0 (1 << 13)
-#define ALLOW_SPXB_CG_INC0 (1 << 12)
-#define BIOS_PCI_EXP_EN (1 << 10)
-#define PWRBTN_LVL (1 << 9)
-#define ALLOW_L1LOW_C0 (1 << 7)
-#define ALLOW_L1LOW_OPI_ON (1 << 6)
-#define SMI_LOCK (1 << 4)
-#define GEN_PMCON_B 0xa4
-#define SLP_STR_POL_LOCK (1 << 18)
-#define ACPI_BASE_LOCK (1 << 17)
-#define SUS_PWR_FLR (1 << 14)
-#define WOL_EN_OVRD (1 << 13)
-#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
-#define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10)
-#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)
-#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)
-#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)
-#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)
-#define HOST_RST_STS (1 << 9)
-#define S4MAW_MASK (0x3 << 4)
-#define S4MAW_1S (1 << 4)
-#define S4MAW_2S (2 << 4)
-#define S4MAW_3S (3 << 4)
-#define S4MAW_4S (0 << 4)
-#define S4ASE (1 << 3)
-#define RTC_BATTERY_DEAD (1 << 2)
-#define PWR_FLR (1 << 1)
-#define SLEEP_AFTER_POWER_FAIL (1 << 0)
-#define ETR3 0xac
-#define ETR3_CF9LOCK (1 << 31)
-#define ETR3_CF9GR (1 << 20)
-
-/* Memory mapped IO registers in PMC */
-#define S3_PWRGATE_POL 0x28
-#define S3DC_GATE_SUS (1 << 1)
-#define S3AC_GATE_SUS (1 << 0)
-#define S4_PWRGATE_POL 0x2c
-#define S4DC_GATE_SUS (1 << 1)
-#define S4AC_GATE_SUS (1 << 0)
-#define S5_PWRGATE_POL 0x30
-#define S5DC_GATE_SUS (1 << 15)
-#define S5AC_GATE_SUS (1 << 14)
-#define DSX_CFG 0x34
-#define DSX_CFG_MASK 0x7
-#define DSX_EN_WAKE_PIN (1 << 2)
-#define DSX_EN_AC_PRESENT_PIN (1 << 1)
-#define DSX_EN_LAN_WAKE_PIN (1 << 0)
-#define PMSYNC_TPR_CFG 0xc4
-#define PMSYNC_LOCK (1 << 31)
-#define GPIO_CFG 0x120
-#define GPE0_DWX_MASK 0xf
-#define GPE0_DW0_SHIFT 0
-#define GPE0_DW1_SHIFT 4
-#define GPE0_DW2_SHIFT 8
-#define GBLRST_CAUSE0 0x124
-#define GBLRST_CAUSE1 0x128
-#define CIR31C 0x31c
-#define XTALSDQDIS (1 << 22)
-#endif
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index ad5ae26..d53cb23 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -30,6 +30,7 @@
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO2_STS 0x06
+#define TCO_STS TCO2_STS
#define TCO2_STS_SECOND_TO 0x02
#define TCO2_STS_BOOT 0x04
#define TCO1_CNT 0x08
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 6e7b197..0e7f691 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -42,7 +42,6 @@
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/pmc.h>
#include <soc/ramstage.h>
#include <soc/pcr_ids.h>
#if IS_ENABLED(CONFIG_CHROMEOS)
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index f3a2681..553980f 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -25,13 +25,13 @@
#include <arch/acpi.h>
#include <cpu/cpu.h>
#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
#include <pc80/mc146818rtc.h>
#include <reg_script.h>
#include <string.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
-#include <soc/pmc.h>
#include <soc/pm.h>
#include <cpu/x86/smm.h>
#include <soc/pcr_ids.h>
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 9b38531..10b0002 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -26,6 +26,7 @@
#include <device/pci.h>
#include <device/pci_def.h>
#include <console/console.h>
+#include <intelblocks/pmclib.h>
#include <halt.h>
#include <rules.h>
#include <stdlib.h>
@@ -35,130 +36,17 @@
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/pmc.h>
#include <soc/smbus.h>
#include <timer.h>
#include "chip.h"
-
-/* Print status bits with descriptive names */
-static void print_status_bits(u32 status, const char * const bit_names[])
-{
- int i;
-
- if (!status)
- return;
-
- for (i = 31; i >= 0; i--) {
- if (status & (1 << i)) {
- if (bit_names[i])
- printk(BIOS_DEBUG, "%s ", bit_names[i]);
- else
- printk(BIOS_DEBUG, "BIT%d ", i);
- }
- }
-}
-
-/* Print status bits as GPIO numbers */
-static void print_gpio_status(u32 status, int start)
-{
- int i;
-
- if (!status)
- return;
-
- for (i = 31; i >= 0; i--) {
- if (status & (1 << i))
- printk(BIOS_DEBUG, "GPIO%d ", start + i);
- }
-}
-
-
-/*
- * PM1_CNT
- */
-
-/* Enable events in PM1 control register */
-void enable_pm1_control(u32 mask)
-{
- u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- pm1_cnt |= mask;
- outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
-}
-
-/* Disable events in PM1 control register */
-void disable_pm1_control(u32 mask)
-{
- u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- pm1_cnt &= ~mask;
- outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
-}
-
-
-/*
- * PM1
- */
-
-/* Clear and return PM1 status register */
-static u16 reset_pm1_status(void)
-{
- u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
- outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS);
- return pm1_sts;
-}
-
-/* Print PM1 status bits */
-static u16 print_pm1_status(u16 pm1_sts)
-{
- static const char * const pm1_sts_bits[] = {
- [0] = "TMROF",
- [4] = "BM",
- [5] = "GBL",
- [8] = "PWRBTN",
- [10] = "RTC",
- [11] = "PRBTNOR",
- [14] = "PCIEXPWAK",
- [15] = "WAK",
- };
-
- if (!pm1_sts)
- return 0;
-
- printk(BIOS_SPEW, "PM1_STS: ");
- print_status_bits(pm1_sts, pm1_sts_bits);
- printk(BIOS_SPEW, "\n");
-
- return pm1_sts;
-}
-
-/* Print, clear, and return PM1 status */
-u16 clear_pm1_status(void)
-{
- return print_pm1_status(reset_pm1_status());
-}
-
-/* Set the PM1 register to events */
-void enable_pm1(u16 events)
-{
- outw(events, ACPI_BASE_ADDRESS + PM1_EN);
-}
-
/*
* SMI
*/
-/* Clear and return SMI status register */
-static u32 reset_smi_status(void)
+const char *const *soc_smi_sts_array(int *a)
{
- u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
- outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
- return smi_sts;
-}
-
-/* Print SMI status bits */
-static u32 print_smi_status(u32 smi_sts)
-{
- static const char * const smi_sts_bits[] = {
+ static const char *const smi_sts_bits[] = {
[2] = "BIOS",
[3] = "LEGACY_USB",
[4] = "SLP_SMI",
@@ -182,70 +70,17 @@
[28] = "ESPI_SMI",
};
- if (!smi_sts)
- return 0;
-
- printk(BIOS_DEBUG, "SMI_STS: ");
- print_status_bits(smi_sts, smi_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return smi_sts;
-}
-
-/* Print, clear, and return SMI status */
-u32 clear_smi_status(void)
-{
- return print_smi_status(reset_smi_status());
-}
-
-/* Enable SMI event */
-void enable_smi(u32 mask)
-{
- u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
- smi_en |= mask;
- outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
-}
-
-/* Disable SMI event */
-void disable_smi(u32 mask)
-{
- u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
- smi_en &= ~mask;
- outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
+ *a = ARRAY_SIZE(smi_sts_bits);
+ return smi_sts_bits;
}
/*
* TCO
*/
-/* Clear TCO status and return events that are enabled and active */
-static u32 reset_tco_status(void)
+const char *const *soc_tco_sts_array(int *a)
{
- u16 tco1_sts;
- u16 tco2_sts;
- u16 tcobase;
-
- tcobase = smbus_tco_regs();
-
- /* TCO Status 2 register*/
- tco2_sts = inw(tcobase + TCO2_STS);
- tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
- outw(tco2_sts, tcobase + TCO2_STS);
-
- /* TCO Status 1 register*/
- tco1_sts = inw(tcobase + TCO1_STS);
-
- /* Clear SECOND_TO_STS bit */
- if (tco2_sts & TCO2_STS_SECOND_TO)
- outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
-
- return (tco2_sts << 16) | tco1_sts;
-}
-
-/* Print TCO status bits */
-static u32 print_tco_status(u32 tco_sts)
-{
- static const char * const tco_sts_bits[] = {
+ static const char *const tco_sts_bits[] = {
[0] = "NMI2SMI",
[1] = "SW_TCO",
[2] = "TCO_INT",
@@ -262,20 +97,8 @@
[20] = "SMLINK_SLV"
};
- if (!tco_sts)
- return 0;
-
- printk(BIOS_DEBUG, "TCO_STS: ");
- print_status_bits(tco_sts, tco_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return tco_sts;
-}
-
-/* Print, clear, and return TCO status */
-u32 clear_tco_status(void)
-{
- return print_tco_status(reset_tco_status());
+ *a = ARRAY_SIZE(tco_sts_bits);
+ return tco_sts_bits;
}
/* Enable TCO SCI */
@@ -285,106 +108,36 @@
outl(TCOSCI_STS, ACPI_BASE_ADDRESS + GPE0_STS(3));
/* Enable TCO SCI events */
- enable_gpe(TCOSCI_EN);
+ pmc_enable_gpe(TCOSCI_EN);
}
-
/*
* GPE0
*/
-/* Clear a GPE0 status and return events that are enabled and active */
-static u32 reset_gpe(u16 sts_reg, u16 en_reg)
+const char *const *soc_gpe_sts_array(int *a)
{
- u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg);
- u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg);
-
- outl(gpe0_sts, ACPI_BASE_ADDRESS + sts_reg);
-
- /* Only report enabled events */
- return gpe0_sts & gpe0_en;
-}
-
-/* Print GPE0 status bits */
-static u32 print_gpe_status(u32 gpe0_sts, const char * const bit_names[])
-{
- if (!gpe0_sts)
- return 0;
-
- printk(BIOS_DEBUG, "GPE0_STS: ");
- print_status_bits(gpe0_sts, bit_names);
- printk(BIOS_DEBUG, "\n");
-
- return gpe0_sts;
-}
-
-/* Print GPE0 GPIO status bits */
-static u32 print_gpe_gpio(u32 gpe0_sts, int start)
-{
- if (!gpe0_sts)
- return 0;
-
- printk(BIOS_DEBUG, "GPE0_STS: ");
- print_gpio_status(gpe0_sts, start);
- printk(BIOS_DEBUG, "\n");
-
- return gpe0_sts;
-}
-
-/* Clear all GPE status and return "standard" GPE event status */
-u32 clear_gpe_status(void)
-{
- static const char * const gpe0_sts_3_bits[] = {
- [1] = "HOTPLUG",
+ static const char *const gpe_sts_bits[] = {
+ [0] = "PCIE_SCI",
[2] = "SWGPE",
- [6] = "TCO_SCI",
- [7] = "SMB_WAK",
+ [3] = "PCIE_WAKE0",
+ [4] = "PUNIT",
+ [6] = "PCIE_WAKE1",
+ [7] = "PCIE_WAKE2",
+ [8] = "PCIE_WAKE3",
[9] = "PCI_EXP",
[10] = "BATLOW",
- [11] = "PME",
- [12] = "ME",
- [13] = "PME_B0",
- [14] = "eSPI",
- [15] = "GPIO Tier-2",
- [16] = "LAN_WAKE",
- [18] = "WADT"
+ [11] = "CSE_PME",
+ [12] = "XDCI_PME",
+ [13] = "XHCI_PME",
+ [14] = "AVS_PME",
+ [15] = "GPIO_TIER1_SCI",
+ [16] = "SMB_WAK",
+ [17] = "SATA_PME",
};
- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);
- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);
- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_95_64), GPE0_EN(GPE_95_64)), 64);
- return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),
- gpe0_sts_3_bits);
-}
-
-/* Read and clear GPE status (defined in arch/acpi.h) */
-int acpi_get_gpe(int gpe)
-{
- int bank;
- uint32_t mask, sts;
- struct stopwatch sw;
- int rc = 0;
-
- if (gpe < 0 || gpe > GPE0_WADT)
- return -1;
-
- bank = gpe / 32;
- mask = 1 << (gpe % 32);
-
- /* Wait up to 1ms for GPE status to clear */
- stopwatch_init_msecs_expire(&sw, 1);
- do {
- if (stopwatch_expired(&sw))
- return rc;
-
- sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
- if (sts & mask) {
- outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
- rc = 1;
- }
- } while (sts & mask);
-
- return rc;
+ *a = ARRAY_SIZE(gpe_sts_bits);
+ return gpe_sts_bits;
}
/* Enable all requested GPE */
@@ -394,28 +147,6 @@
outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32));
outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_95_64));
outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
-}
-
-/* Disable all GPE */
-void disable_all_gpe(void)
-{
- enable_all_gpe(0, 0, 0, 0);
-}
-
-/* Enable a standard GPE */
-void enable_gpe(u32 mask)
-{
- u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
- gpe0_en |= mask;
- outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
-}
-
-/* Disable a standard GPE */
-void disable_gpe(u32 mask)
-{
- u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
- gpe0_en &= ~mask;
- outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
}
int acpi_sci_irq(void)
@@ -455,7 +186,12 @@
/* 4KiB alignment. */
reg32 &= ~0xfff;
- return (void *)(uintptr_t)reg32;
+ return (void *)(uintptr_t) reg32;
+}
+
+uint16_t soc_tco_base(void)
+{
+ return (uintptr_t) (smbus_tco_regs());
}
uint16_t smbus_tco_regs(void)
@@ -469,59 +205,50 @@
return reg16;
}
-void poweroff(void)
+uint32_t soc_reset_tco(void)
{
- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ u16 tco1_sts;
+ u16 tco2_sts;
+ u16 tcobase;
- /*
- * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM
- * to transition to S5 state. If halt is called in SMM, then it prevents
- * the SMI handler from being triggered and system never enters S5.
- */
- if (!ENV_SMM)
- halt();
+ tcobase = smbus_tco_regs();
+
+ /* TCO Status 2 register */
+ tco2_sts = inw(tcobase + TCO2_STS);
+ tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
+ outw(tco2_sts, tcobase + TCO2_STS);
+
+ /* TCO Status 1 register */
+ tco1_sts = inw(tcobase + TCO1_STS);
+
+ /* Clear SECOND_TO_STS bit */
+ if (tco2_sts & TCO2_STS_SECOND_TO)
+ outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
+
+ return (tco2_sts << 16) | tco1_sts;
}
-void pmc_gpe_init(void)
+uintptr_t soc_read_pmc_base(void)
+{
+ return (uintptr_t) (pmc_mmio_regs());
+}
+
+uint8_t soc_get_devicetree_info(int8_t *dw0, int8_t *dw1, int8_t *dw2)
{
DEVTREE_CONST struct soc_intel_skylake_config *config;
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
- uint8_t *pmc_regs;
- uint32_t gpio_cfg;
- uint32_t gpio_cfg_reg;
- const uint32_t gpio_cfg_mask =
- (GPE0_DWX_MASK << GPE0_DW0_SHIFT) |
- (GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
- (GPE0_DWX_MASK << GPE0_DW2_SHIFT);
/* Look up the device in devicetree */
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
- return;
+ return -1;
}
config = dev->chip_info;
- pmc_regs = pmc_mmio_regs();
- /* Route the GPIOs to the GPE0 block. Determine that all values
- * are different, and if they aren't use the reset values. */
- gpio_cfg = 0;
- if (config->gpe0_dw0 == config->gpe0_dw1 ||
- config->gpe0_dw1 == config->gpe0_dw2) {
- printk(BIOS_INFO, "PMC: Using default GPE route.\n");
- gpio_cfg = read32(pmc_regs + GPIO_CFG);
- } else {
- gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT;
- gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT;
- gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT;
- }
- gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask;
- gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
- write32(pmc_regs + GPIO_CFG, gpio_cfg_reg);
+ /* Assign to out variable */
+ *dw0 = config->gpe0_dw0;
+ *dw1 = config->gpe0_dw1;
+ *dw2 = config->gpe0_dw2;
- /* Set the routes in the GPIO communities as well. */
- gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT);
-
- /* Set GPE enables based on devictree. */
- enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
- config->gpe0_en_3, config->gpe0_en_4);
+ return 0;
}
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index 6910914..1fc76ac 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -32,9 +32,9 @@
* PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
*/
pmc_regs = pmc_mmio_regs();
- reg32 = read32(pmc_regs + ETR3);
- reg32 |= ETR3_CF9GR;
- write32(pmc_regs + ETR3, reg32);
+ reg32 = read32(pmc_regs + ETR);
+ reg32 |= CF9_GLB_RST;
+ write32(pmc_regs + ETR, reg32);
/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
* to global reset platform */
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 61851a5..6cf2104 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -26,12 +26,12 @@
#include <stdlib.h>
#include <string.h>
#include <soc/iomap.h>
-#include <soc/pmc.h>
#include <soc/smbus.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <vboot/vboot_common.h>
+#include <intelblocks/pmclib.h>
static struct chipset_power_state power_state CAR_GLOBAL;
@@ -49,42 +49,28 @@
}
memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
}
+
ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
/* Return 0, 3, or 5 to indicate the previous sleep state. */
-static uint32_t prev_sleep_state(struct chipset_power_state *ps)
+void chipset_prev_sleep_state(struct chipset_power_state *ps,
+ int *prev_sleep_state)
{
- /* Default to S0. */
- uint32_t prev_sleep_state = ACPI_S0;
- if (ps->pm1_sts & WAK_STS) {
- switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
- case ACPI_S3:
- if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
- prev_sleep_state = ACPI_S3;
- break;
- case ACPI_S5:
- prev_sleep_state = ACPI_S5;
- break;
- }
- /* Clear SLP_TYP. */
- outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
- } else {
- /*
- * Check for any power failure to determine if this a wake from
- * S5 because the PCH does not set the WAK_STS bit when waking
- * from a true G3 state.
- */
- if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
- prev_sleep_state = ACPI_S5;
- }
+ /*
+ * Check for any power failure to determine if this a wake from
+ * S5 because the PCH does not set the WAK_STS bit when waking
+ * from a true G3 state.
+ */
+ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
+ *prev_sleep_state = ACPI_S5;
/*
* If waking from S3 determine if deep S3 is enabled. If not,
* need to check both deep sleep well and normal suspend well.
* Otherwise just check deep sleep well.
*/
- if (prev_sleep_state == ACPI_S3) {
+ if (*prev_sleep_state == ACPI_S3) {
/* PWR_FLR represents deep sleep power well loss. */
uint32_t mask = PWR_FLR;
@@ -93,59 +79,27 @@
mask |= SUS_PWR_FLR;
if (ps->gen_pmcon_b & mask)
- prev_sleep_state = ACPI_S5;
+ *prev_sleep_state = ACPI_S5;
}
-
- return prev_sleep_state;
}
-static void dump_power_state(struct chipset_power_state *ps)
-{
- printk(BIOS_DEBUG, "PM1_STS: %04x\n", ps->pm1_sts);
- printk(BIOS_DEBUG, "PM1_EN: %04x\n", ps->pm1_en);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", ps->pm1_cnt);
- printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
- ps->tco1_sts, ps->tco2_sts);
-
- printk(BIOS_DEBUG, "GPE0_STS: %08x %08x %08x %08x\n",
- ps->gpe0_sts[0], ps->gpe0_sts[1],
- ps->gpe0_sts[2], ps->gpe0_sts[3]);
- printk(BIOS_DEBUG, "GPE0_EN: %08x %08x %08x %08x\n",
- ps->gpe0_en[0], ps->gpe0_en[1],
- ps->gpe0_en[2], ps->gpe0_en[3]);
-
- printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
- ps->gen_pmcon_a, ps->gen_pmcon_b);
-
- printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
- ps->gblrst_cause[0], ps->gblrst_cause[1]);
-
- printk(BIOS_DEBUG, "Previous Sleep State: S%d\n",
- ps->prev_sleep_state);
-}
-
-/* Fill power state structure from ACPI PM registers */
-struct chipset_power_state *fill_power_state(void)
+int soc_fill_power_state(void)
{
uint16_t tcobase;
uint8_t *pmc;
- struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+ struct chipset_power_state *ps;
+
+ ps = car_get_var_ptr(&power_state);
+
+ pmc_fill_power_state(ps);
tcobase = smbus_tco_regs();
- ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
- ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
- ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
ps->tco1_sts = inw(tcobase + TCO1_STS);
ps->tco2_sts = inw(tcobase + TCO2_STS);
- ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
- ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
- ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
- ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
- ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
- ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
- ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
- ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
+
+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
+ ps->tco1_sts, ps->tco2_sts);
ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
@@ -154,28 +108,11 @@
ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
- ps->prev_sleep_state = prev_sleep_state(ps);
+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
+ ps->gen_pmcon_a, ps->gen_pmcon_b);
- dump_power_state(ps);
+ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
+ ps->gblrst_cause[0], ps->gblrst_cause[1]);
- return ps;
-}
-
-int vboot_platform_is_resuming(void)
-{
- return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
-}
-
-/*
- * The PM1 control is set to S5 when vboot requests a reboot because the power
- * state code above may not have collected it's data yet. Therefore, set it to
- * S5 when vboot requests a reboot. That's necessary if vboot fails in the
- * resume path and requests a reboot. This prevents a reboot loop where the
- * error is continually hit on the failing vboot resume path.
- */
-void vboot_platform_prepare_reboot(void)
-{
- uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;
-
- outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
+ return ps->prev_sleep_state;
}
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index cb704fd..e2e3921 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -34,7 +34,6 @@
#include <soc/pci_devs.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h>
-#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/romstage.h>
#include <stage_cache.h>
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 4530190..69a0934 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -120,16 +120,14 @@
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
- struct chipset_power_state *ps;
+ //struct chipset_power_state *ps;
console_init();
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
-
- ps = fill_power_state();
timestamp_add_now(TS_START_ROMSTAGE);
- s3wake = ps->prev_sleep_state == ACPI_S3;
+ s3wake = soc_fill_power_state() == ACPI_S3;
fsp_memory_init(s3wake);
pmc_set_disb();
if (!s3wake)
diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c
index 7343637..7315a76 100644
--- a/src/soc/intel/skylake/smi.c
+++ b/src/soc/intel/skylake/smi.c
@@ -27,6 +27,7 @@
#include <soc/pch.h>
#include <soc/pm.h>
#include <soc/smm.h>
+#include <intelblocks/pmclib.h>
void southbridge_smm_clear_state(void)
{
@@ -44,18 +45,18 @@
printk(BIOS_DEBUG, "\n");
/* Dump and clear status registers */
- clear_smi_status();
- clear_pm1_status();
- clear_tco_status();
- clear_gpe_status();
+ pmc_clear_smi_status();
+ pmc_clear_pm1_status();
+ pmc_clear_tco_status();
+ pmc_clear_gpe_status();
}
void southbridge_smm_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events */
- enable_pm1(PWRBTN_EN | GBL_EN);
- disable_gpe(PME_B0_EN);
+ pmc_enable_pm1(PWRBTN_EN | GBL_EN);
+ pmc_disable_gpe(PME_B0_EN);
/*
* Enable SMI generation:
@@ -67,7 +68,7 @@
* - on microcontroller writes (io 0x62/0x66)
* - on TCO events
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);
+ pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index c4c4a7b..2d20cc0 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -24,6 +24,7 @@
#include <elog.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
#include <delay.h>
#include <device/pci_def.h>
#include <elog.h>
@@ -36,7 +37,6 @@
#include <soc/pch.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#include <soc/pmc.h>
#include <soc/smm.h>
#include <types.h>
@@ -81,7 +81,7 @@
/* Set the EOS bit */
void southbridge_smi_set_eos(void)
{
- enable_smi(EOS);
+ pmc_enable_smi(EOS);
}
static void busmaster_disable_on_bus(int bus)
@@ -136,7 +136,7 @@
outb(tmp72, 0x72);
/* First, disable further SMIs */
- disable_smi(SLP_SMI_EN);
+ pmc_disable_smi(SLP_SMI_EN);
/* Figure out SLP_TYP */
reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
@@ -152,7 +152,7 @@
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
/* Clear pending GPE events */
- clear_gpe_status();
+ pmc_clear_gpe_status();
/* Next, do the deed. */
switch (slp_typ) {
@@ -173,7 +173,7 @@
/*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/
s5pwr = MAINBOARD_POWER_ON;
/* Disable all GPE */
- disable_all_gpe();
+ pmc_disable_all_gpe();
/*
* Always set the flag in case CMOS was changed on runtime. For
@@ -199,7 +199,7 @@
* event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
- enable_pm1_control(SLP_EN);
+ pmc_enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ >= ACPI_S3)
@@ -213,7 +213,7 @@
reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
- disable_pm1_control(SLP_EN | SLP_TYP);
+ pmc_disable_pm1_control(SLP_EN | SLP_TYP);
}
}
@@ -304,11 +304,11 @@
printk(BIOS_DEBUG, "P-state control\n");
break;
case APM_CNT_ACPI_DISABLE:
- disable_pm1_control(SCI_EN);
+ pmc_disable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
- enable_pm1_control(SCI_EN);
+ pmc_enable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_FINALIZE:
@@ -339,7 +339,7 @@
static void southbridge_smi_pm1(void)
{
- u16 pm1_sts = clear_pm1_status();
+ u16 pm1_sts = pmc_clear_pm1_status();
/*
* While OSPM is not active, poweroff immediately on a power button
@@ -349,14 +349,14 @@
/* power button pressed */
if (IS_ENABLED(CONFIG_ELOG_GSMI))
elog_add_event(ELOG_TYPE_POWER_BUTTON);
- disable_pm1_control(-1UL);
- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
+ pmc_disable_pm1_control(-1UL);
+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
}
}
static void southbridge_smi_gpe0(void)
{
- clear_gpe_status();
+ pmc_clear_gpe_status();
}
void __attribute__((weak))
@@ -392,7 +392,7 @@
static void southbridge_smi_tco(void)
{
- u32 tco_sts = clear_tco_status();
+ u32 tco_sts = pmc_clear_tco_status();
/* Any TCO event? */
if (!tco_sts)
@@ -520,7 +520,7 @@
* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
- smi_sts = clear_smi_status();
+ smi_sts = pmc_clear_smi_status();
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
--
To view, visit https://review.coreboot.org/20219
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If7be9860bdd7d825bb7302168501129f09ca4741
Gerrit-Change-Number: 20219
Gerrit-PatchSet: 1
Gerrit-Owner: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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