<p>Shaunak Saha has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20219">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]soc/intel/skylake: Add support in SKL for PMC common code<br><br>Change-Id: If7be9860bdd7d825bb7302168501129f09ca4741<br>Signed-off-by: Shaunak Saha <shaunak.saha@intel.com><br>---<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/bootblock/pch.c<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/include/soc/gpe.h<br>M src/soc/intel/skylake/include/soc/pm.h<br>D src/soc/intel/skylake/include/soc/pmc.h<br>M src/soc/intel/skylake/include/soc/smbus.h<br>M src/soc/intel/skylake/lpc.c<br>M src/soc/intel/skylake/pmc.c<br>M src/soc/intel/skylake/pmutil.c<br>M src/soc/intel/skylake/reset.c<br>M src/soc/intel/skylake/romstage/power_state.c<br>M src/soc/intel/skylake/romstage/romstage.c<br>M src/soc/intel/skylake/romstage/romstage_fsp20.c<br>M src/soc/intel/skylake/smi.c<br>M src/soc/intel/skylake/smihandler.c<br>16 files changed, 234 insertions(+), 585 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/20219/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig<br>index 26f9021..b59f9c9 100644<br>--- a/src/soc/intel/skylake/Kconfig<br>+++ b/src/soc/intel/skylake/Kconfig<br>@@ -59,6 +59,7 @@<br> select SOC_INTEL_COMMON_BLOCK_I2C<br> select SOC_INTEL_COMMON_BLOCK_LPSS<br> select SOC_INTEL_COMMON_BLOCK_PCIE<br>+ select SOC_INTEL_COMMON_BLOCK_PMC<br> select SOC_INTEL_COMMON_BLOCK_PCR<br> select SOC_INTEL_COMMON_BLOCK_RTC<br> select SOC_INTEL_COMMON_BLOCK_SA<br>diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c<br>index 780c4aa..750463c 100644<br>--- a/src/soc/intel/skylake/bootblock/pch.c<br>+++ b/src/soc/intel/skylake/bootblock/pch.c<br>@@ -22,6 +22,7 @@<br> #include <intelblocks/itss.h><br> #include <intelblocks/pcr.h><br> #include <intelblocks/rtc.h><br>+#include <intelblocks/pmclib.h><br> #include <intelblocks/smbus.h><br> #include <soc/bootblock.h><br> #include <soc/iomap.h><br>@@ -31,7 +32,6 @@<br> #include <soc/pci_devs.h><br> #include <soc/pcr_ids.h><br> #include <soc/pm.h><br>-#include <soc/pmc.h><br> #include <soc/smbus.h><br> <br> #define PCR_DMI_LPCLGIR1 0x2730<br>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h<br>index b4f6545..0231110 100644<br>--- a/src/soc/intel/skylake/chip.h<br>+++ b/src/soc/intel/skylake/chip.h<br>@@ -28,10 +28,10 @@<br> #include <soc/gpe.h><br> #include <soc/irq.h><br> #include <soc/pci_devs.h><br>-#include <soc/pmc.h><br> #include <soc/serialio.h><br> #include <soc/usb.h><br> #include <soc/vr_config.h><br>+#include <soc/pm.h><br> <br> #define SKYLAKE_I2C_DEV_MAX 6<br> <br>diff --git a/src/soc/intel/skylake/include/soc/gpe.h b/src/soc/intel/skylake/include/soc/gpe.h<br>index 655cc11..d0962b8 100644<br>--- a/src/soc/intel/skylake/include/soc/gpe.h<br>+++ b/src/soc/intel/skylake/include/soc/gpe.h<br>@@ -130,4 +130,6 @@<br> #define GPE0_LAN_WAK 112<br> #define GPE0_WADT 114<br> <br>+#define GPE_MAX GPE0_WADT<br>+<br> #endif /* _SOC_GPE_H_ */<br>diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h<br>index 15c291c..bf99734 100644<br>--- a/src/soc/intel/skylake/include/soc/pm.h<br>+++ b/src/soc/intel/skylake/include/soc/pm.h<br>@@ -19,7 +19,7 @@<br> <br> #include <arch/acpi.h><br> #include <arch/io.h><br>-#include <soc/pmc.h><br>+#include <soc/smbus.h><br> <br> /* ACPI_BASE_ADDRESS / PMBASE */<br> <br>@@ -135,6 +135,94 @@<br> #define MAINBOARD_POWER_ON 1<br> #define MAINBOARD_POWER_KEEP 2<br> <br>+#define EN_BLOCK 3<br>+<br>+/* PCI Configuration Space (D31:F2): PMC */<br>+#define ABASE 0x40<br>+#define ACTL 0x44<br>+#define PWRM_EN (1 << 8)<br>+#define ACPI_EN (1 << 7)<br>+#define SCI_IRQ_SEL (7 << 0)<br>+#define SCIS_IRQ9 0<br>+#define SCIS_IRQ10 1<br>+#define SCIS_IRQ11 2<br>+#define SCIS_IRQ20 4<br>+#define SCIS_IRQ21 5<br>+#define SCIS_IRQ22 6<br>+#define SCIS_IRQ23 7<br>+#define PWRMBASE 0x48<br>+#define GEN_PMCON_A 0xa0<br>+#define DC_PP_DIS (1 << 30)<br>+#define DSX_PP_DIS (1 << 29)<br>+#define AG3_PP_EN (1 << 28)<br>+#define SX_PP_EN (1 << 27)<br>+#define DISB (1 << 23)<br>+#define MEM_SR (1 << 21)<br>+#define MS4V (1 << 18)<br>+#define GBL_RST_STS (1 << 16)<br>+#define ALLOW_ICLK_PLL_SD_INC0 (1 << 15)<br>+#define MPHY_CRICLK_GATE_OVER (1 << 14)<br>+#define ALLOW_OPI_PLL_SD_INC0 (1 << 13)<br>+#define ALLOW_SPXB_CG_INC0 (1 << 12)<br>+#define BIOS_PCI_EXP_EN (1 << 10)<br>+#define PWRBTN_LVL (1 << 9)<br>+#define ALLOW_L1LOW_C0 (1 << 7)<br>+#define ALLOW_L1LOW_OPI_ON (1 << 6)<br>+#define SMI_LOCK (1 << 4)<br>+#define GEN_PMCON_B 0xa4<br>+#define SLP_STR_POL_LOCK (1 << 18)<br>+#define ACPI_BASE_LOCK (1 << 17)<br>+#define SUS_PWR_FLR (1 << 14)<br>+#define WOL_EN_OVRD (1 << 13)<br>+#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)<br>+#define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10)<br>+#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)<br>+#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)<br>+#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)<br>+#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)<br>+#define HOST_RST_STS (1 << 9)<br>+#define S4MAW_MASK (0x3 << 4)<br>+#define S4MAW_1S (1 << 4)<br>+#define S4MAW_2S (2 << 4)<br>+#define S4MAW_3S (3 << 4)<br>+#define S4MAW_4S (0 << 4)<br>+#define S4ASE (1 << 3)<br>+#define RTC_BATTERY_DEAD (1 << 2)<br>+#define PWR_FLR (1 << 1)<br>+#define SLEEP_AFTER_POWER_FAIL (1 << 0)<br>+/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */<br>+#define ETR 0xac<br>+# define CF9_LOCK (1 << 31)<br>+# define CF9_GLB_RST (1 << 20)<br>+<br>+/* Memory mapped IO registers in PMC */<br>+#define S3_PWRGATE_POL 0x28<br>+#define S3DC_GATE_SUS (1 << 1)<br>+#define S3AC_GATE_SUS (1 << 0)<br>+#define S4_PWRGATE_POL 0x2c<br>+#define S4DC_GATE_SUS (1 << 1)<br>+#define S4AC_GATE_SUS (1 << 0)<br>+#define S5_PWRGATE_POL 0x30<br>+#define S5DC_GATE_SUS (1 << 15)<br>+#define S5AC_GATE_SUS (1 << 14)<br>+#define DSX_CFG 0x34<br>+#define DSX_CFG_MASK 0x7<br>+#define DSX_EN_WAKE_PIN (1 << 2)<br>+#define DSX_EN_AC_PRESENT_PIN (1 << 1)<br>+#define DSX_EN_LAN_WAKE_PIN (1 << 0)<br>+#define PMSYNC_TPR_CFG 0xc4<br>+#define PMSYNC_LOCK (1 << 31)<br>+#define GPIO_GPE_CFG 0x120<br>+#define GPE0_DWX_MASK 0xf<br>+#define GPE0_DW0_SHIFT 0<br>+#define GPE0_DW1_SHIFT 4<br>+#define GPE0_DW2_SHIFT 8<br>+#define GBLRST_CAUSE0 0x124<br>+#define GBLRST_CAUSE1 0x128<br>+#define CIR31C 0x31c<br>+#define XTALSDQDIS (1 << 22)<br>+#define PRSTS 0x10<br>+<br> struct chipset_power_state {<br> uint16_t pm1_sts;<br> uint16_t pm1_en;<br>@@ -149,46 +237,45 @@<br> uint32_t prev_sleep_state;<br> } __attribute__ ((packed));<br> <br>-struct chipset_power_state *fill_power_state(void);<br>-<br>-/* PM1_CNT */<br>-void enable_pm1_control(uint32_t mask);<br>-void disable_pm1_control(uint32_t mask);<br>-<br>-/* PM1 */<br>-uint16_t clear_pm1_status(void);<br>-void enable_pm1(uint16_t events);<br>-uint32_t clear_smi_status(void);<br>-<br>-/* SMI */<br>-void enable_smi(uint32_t mask);<br>-void disable_smi(uint32_t mask);<br> <br> /* TCO */<br>-uint32_t clear_tco_status(void);<br> void enable_tco_sci(void);<br> <br> /* GPE0 */<br> uint32_t clear_gpe_status(void);<br> void clear_gpe_enable(void);<br> void enable_all_gpe(uint32_t set1, uint32_t set2, uint32_t set3, uint32_t set4);<br>-void disable_all_gpe(void);<br>-void enable_gpe(uint32_t mask);<br>-void disable_gpe(uint32_t mask);<br> <br> /* Return the selected ACPI SCI IRQ */<br> int acpi_sci_irq(void);<br> <br> /* Get base address PMC memory mapped registers. */<br> uint8_t *pmc_mmio_regs(void);<br>+uintptr_t soc_read_pmc_base(void);<br>+void soc_clear_status(uintptr_t pmc_bar);<br> /* Get base address of TCO I/O registers. */<br> uint16_t smbus_tco_regs(void);<br>+uint16_t soc_tco_base(void);<br>+uint32_t soc_reset_tco(void);<br> <br> /* Set the DISB after DRAM init */<br> void pmc_set_disb(void);<br> <br> /* Initialize GPEs */<br>-void pmc_gpe_init(void);<br>+uint8_t soc_get_devicetree_info(int8_t *dw0, int8_t *dw1, int8_t *dw2);<br>+<br>+int soc_fill_power_state(void);<br>+<br>+void chipset_prev_sleep_state(struct chipset_power_state *ps,<br>+ int *prev_sleep_state);<br>+<br>+<br>+const char * const *soc_gpe_sts_array(int *a);<br>+const char * const *soc_smi_sts_array(int *a);<br>+const char * const *soc_tco_sts_array(int *a);<br>+<br>+void global_reset_lock(void);<br>+void global_reset_enable(bool enable);<br> <br> static inline int deep_s3_enabled(void)<br> {<br>diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h<br>deleted file mode 100644<br>index 4a80917..0000000<br>--- a/src/soc/intel/skylake/include/soc/pmc.h<br>+++ /dev/null<br>@@ -1,103 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2014 Google Inc.<br>- * Copyright (C) 2015 Intel Corporation.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef _SOC_PMC_H_<br>-#define _SOC_PMC_H_<br>-<br>-/* PCI Configuration Space (D31:F2): PMC */<br>-#define ABASE 0x40<br>-#define ACTL 0x44<br>-#define PWRM_EN (1 << 8)<br>-#define ACPI_EN (1 << 7)<br>-#define SCI_IRQ_SEL (7 << 0)<br>-#define SCIS_IRQ9 0<br>-#define SCIS_IRQ10 1<br>-#define SCIS_IRQ11 2<br>-#define SCIS_IRQ20 4<br>-#define SCIS_IRQ21 5<br>-#define SCIS_IRQ22 6<br>-#define SCIS_IRQ23 7<br>-#define PWRMBASE 0x48<br>-#define GEN_PMCON_A 0xa0<br>-#define DC_PP_DIS (1 << 30)<br>-#define DSX_PP_DIS (1 << 29)<br>-#define AG3_PP_EN (1 << 28)<br>-#define SX_PP_EN (1 << 27)<br>-#define DISB (1 << 23)<br>-#define MEM_SR (1 << 21)<br>-#define MS4V (1 << 18)<br>-#define GBL_RST_STS (1 << 16)<br>-#define ALLOW_ICLK_PLL_SD_INC0 (1 << 15)<br>-#define MPHY_CRICLK_GATE_OVER (1 << 14)<br>-#define ALLOW_OPI_PLL_SD_INC0 (1 << 13)<br>-#define ALLOW_SPXB_CG_INC0 (1 << 12)<br>-#define BIOS_PCI_EXP_EN (1 << 10)<br>-#define PWRBTN_LVL (1 << 9)<br>-#define ALLOW_L1LOW_C0 (1 << 7)<br>-#define ALLOW_L1LOW_OPI_ON (1 << 6)<br>-#define SMI_LOCK (1 << 4)<br>-#define GEN_PMCON_B 0xa4<br>-#define SLP_STR_POL_LOCK (1 << 18)<br>-#define ACPI_BASE_LOCK (1 << 17)<br>-#define SUS_PWR_FLR (1 << 14)<br>-#define WOL_EN_OVRD (1 << 13)<br>-#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)<br>-#define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10)<br>-#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)<br>-#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)<br>-#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)<br>-#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)<br>-#define HOST_RST_STS (1 << 9)<br>-#define S4MAW_MASK (0x3 << 4)<br>-#define S4MAW_1S (1 << 4)<br>-#define S4MAW_2S (2 << 4)<br>-#define S4MAW_3S (3 << 4)<br>-#define S4MAW_4S (0 << 4)<br>-#define S4ASE (1 << 3)<br>-#define RTC_BATTERY_DEAD (1 << 2)<br>-#define PWR_FLR (1 << 1)<br>-#define SLEEP_AFTER_POWER_FAIL (1 << 0)<br>-#define ETR3 0xac<br>-#define ETR3_CF9LOCK (1 << 31)<br>-#define ETR3_CF9GR (1 << 20)<br>-<br>-/* Memory mapped IO registers in PMC */<br>-#define S3_PWRGATE_POL 0x28<br>-#define S3DC_GATE_SUS (1 << 1)<br>-#define S3AC_GATE_SUS (1 << 0)<br>-#define S4_PWRGATE_POL 0x2c<br>-#define S4DC_GATE_SUS (1 << 1)<br>-#define S4AC_GATE_SUS (1 << 0)<br>-#define S5_PWRGATE_POL 0x30<br>-#define S5DC_GATE_SUS (1 << 15)<br>-#define S5AC_GATE_SUS (1 << 14)<br>-#define DSX_CFG 0x34<br>-#define DSX_CFG_MASK 0x7<br>-#define DSX_EN_WAKE_PIN (1 << 2)<br>-#define DSX_EN_AC_PRESENT_PIN (1 << 1)<br>-#define DSX_EN_LAN_WAKE_PIN (1 << 0)<br>-#define PMSYNC_TPR_CFG 0xc4<br>-#define PMSYNC_LOCK (1 << 31)<br>-#define GPIO_CFG 0x120<br>-#define GPE0_DWX_MASK 0xf<br>-#define GPE0_DW0_SHIFT 0<br>-#define GPE0_DW1_SHIFT 4<br>-#define GPE0_DW2_SHIFT 8<br>-#define GBLRST_CAUSE0 0x124<br>-#define GBLRST_CAUSE1 0x128<br>-#define CIR31C 0x31c<br>-#define XTALSDQDIS (1 << 22)<br>-#endif<br>diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h<br>index ad5ae26..d53cb23 100644<br>--- a/src/soc/intel/skylake/include/soc/smbus.h<br>+++ b/src/soc/intel/skylake/include/soc/smbus.h<br>@@ -30,6 +30,7 @@<br> /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */<br> #define TCO1_STS 0x04<br> #define TCO2_STS 0x06<br>+#define TCO_STS TCO2_STS<br> #define TCO2_STS_SECOND_TO 0x02<br> #define TCO2_STS_BOOT 0x04<br> #define TCO1_CNT 0x08<br>diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c<br>index 6e7b197..0e7f691 100644<br>--- a/src/soc/intel/skylake/lpc.c<br>+++ b/src/soc/intel/skylake/lpc.c<br>@@ -42,7 +42,6 @@<br> #include <soc/pch.h><br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br>-#include <soc/pmc.h><br> #include <soc/ramstage.h><br> #include <soc/pcr_ids.h><br> #if IS_ENABLED(CONFIG_CHROMEOS)<br>diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c<br>index f3a2681..553980f 100644<br>--- a/src/soc/intel/skylake/pmc.c<br>+++ b/src/soc/intel/skylake/pmc.c<br>@@ -25,13 +25,13 @@<br> #include <arch/acpi.h><br> #include <cpu/cpu.h><br> #include <intelblocks/pcr.h><br>+#include <intelblocks/pmclib.h><br> #include <pc80/mc146818rtc.h><br> #include <reg_script.h><br> #include <string.h><br> #include <soc/gpio.h><br> #include <soc/iomap.h><br> #include <soc/pci_devs.h><br>-#include <soc/pmc.h><br> #include <soc/pm.h><br> #include <cpu/x86/smm.h><br> #include <soc/pcr_ids.h><br>diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c<br>index 9b38531..10b0002 100644<br>--- a/src/soc/intel/skylake/pmutil.c<br>+++ b/src/soc/intel/skylake/pmutil.c<br>@@ -26,6 +26,7 @@<br> #include <device/pci.h><br> #include <device/pci_def.h><br> #include <console/console.h><br>+#include <intelblocks/pmclib.h><br> #include <halt.h><br> #include <rules.h><br> #include <stdlib.h><br>@@ -35,130 +36,17 @@<br> #include <soc/lpc.h><br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br>-#include <soc/pmc.h><br> #include <soc/smbus.h><br> #include <timer.h><br> #include "chip.h"<br>-<br>-/* Print status bits with descriptive names */<br>-static void print_status_bits(u32 status, const char * const bit_names[])<br>-{<br>- int i;<br>-<br>- if (!status)<br>- return;<br>-<br>- for (i = 31; i >= 0; i--) {<br>- if (status & (1 << i)) {<br>- if (bit_names[i])<br>- printk(BIOS_DEBUG, "%s ", bit_names[i]);<br>- else<br>- printk(BIOS_DEBUG, "BIT%d ", i);<br>- }<br>- }<br>-}<br>-<br>-/* Print status bits as GPIO numbers */<br>-static void print_gpio_status(u32 status, int start)<br>-{<br>- int i;<br>-<br>- if (!status)<br>- return;<br>-<br>- for (i = 31; i >= 0; i--) {<br>- if (status & (1 << i))<br>- printk(BIOS_DEBUG, "GPIO%d ", start + i);<br>- }<br>-}<br>-<br>-<br>-/*<br>- * PM1_CNT<br>- */<br>-<br>-/* Enable events in PM1 control register */<br>-void enable_pm1_control(u32 mask)<br>-{<br>- u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);<br>- pm1_cnt |= mask;<br>- outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);<br>-}<br>-<br>-/* Disable events in PM1 control register */<br>-void disable_pm1_control(u32 mask)<br>-{<br>- u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);<br>- pm1_cnt &= ~mask;<br>- outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);<br>-}<br>-<br>-<br>-/*<br>- * PM1<br>- */<br>-<br>-/* Clear and return PM1 status register */<br>-static u16 reset_pm1_status(void)<br>-{<br>- u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);<br>- outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS);<br>- return pm1_sts;<br>-}<br>-<br>-/* Print PM1 status bits */<br>-static u16 print_pm1_status(u16 pm1_sts)<br>-{<br>- static const char * const pm1_sts_bits[] = {<br>- [0] = "TMROF",<br>- [4] = "BM",<br>- [5] = "GBL",<br>- [8] = "PWRBTN",<br>- [10] = "RTC",<br>- [11] = "PRBTNOR",<br>- [14] = "PCIEXPWAK",<br>- [15] = "WAK",<br>- };<br>-<br>- if (!pm1_sts)<br>- return 0;<br>-<br>- printk(BIOS_SPEW, "PM1_STS: ");<br>- print_status_bits(pm1_sts, pm1_sts_bits);<br>- printk(BIOS_SPEW, "\n");<br>-<br>- return pm1_sts;<br>-}<br>-<br>-/* Print, clear, and return PM1 status */<br>-u16 clear_pm1_status(void)<br>-{<br>- return print_pm1_status(reset_pm1_status());<br>-}<br>-<br>-/* Set the PM1 register to events */<br>-void enable_pm1(u16 events)<br>-{<br>- outw(events, ACPI_BASE_ADDRESS + PM1_EN);<br>-}<br>-<br> <br> /*<br> * SMI<br> */<br> <br>-/* Clear and return SMI status register */<br>-static u32 reset_smi_status(void)<br>+const char *const *soc_smi_sts_array(int *a)<br> {<br>- u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);<br>- outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);<br>- return smi_sts;<br>-}<br>-<br>-/* Print SMI status bits */<br>-static u32 print_smi_status(u32 smi_sts)<br>-{<br>- static const char * const smi_sts_bits[] = {<br>+ static const char *const smi_sts_bits[] = {<br> [2] = "BIOS",<br> [3] = "LEGACY_USB",<br> [4] = "SLP_SMI",<br>@@ -182,70 +70,17 @@<br> [28] = "ESPI_SMI",<br> };<br> <br>- if (!smi_sts)<br>- return 0;<br>-<br>- printk(BIOS_DEBUG, "SMI_STS: ");<br>- print_status_bits(smi_sts, smi_sts_bits);<br>- printk(BIOS_DEBUG, "\n");<br>-<br>- return smi_sts;<br>-}<br>-<br>-/* Print, clear, and return SMI status */<br>-u32 clear_smi_status(void)<br>-{<br>- return print_smi_status(reset_smi_status());<br>-}<br>-<br>-/* Enable SMI event */<br>-void enable_smi(u32 mask)<br>-{<br>- u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);<br>- smi_en |= mask;<br>- outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);<br>-}<br>-<br>-/* Disable SMI event */<br>-void disable_smi(u32 mask)<br>-{<br>- u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);<br>- smi_en &= ~mask;<br>- outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);<br>+ *a = ARRAY_SIZE(smi_sts_bits);<br>+ return smi_sts_bits;<br> }<br> <br> /*<br> * TCO<br> */<br> <br>-/* Clear TCO status and return events that are enabled and active */<br>-static u32 reset_tco_status(void)<br>+const char *const *soc_tco_sts_array(int *a)<br> {<br>- u16 tco1_sts;<br>- u16 tco2_sts;<br>- u16 tcobase;<br>-<br>- tcobase = smbus_tco_regs();<br>-<br>- /* TCO Status 2 register*/<br>- tco2_sts = inw(tcobase + TCO2_STS);<br>- tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);<br>- outw(tco2_sts, tcobase + TCO2_STS);<br>-<br>- /* TCO Status 1 register*/<br>- tco1_sts = inw(tcobase + TCO1_STS);<br>-<br>- /* Clear SECOND_TO_STS bit */<br>- if (tco2_sts & TCO2_STS_SECOND_TO)<br>- outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);<br>-<br>- return (tco2_sts << 16) | tco1_sts;<br>-}<br>-<br>-/* Print TCO status bits */<br>-static u32 print_tco_status(u32 tco_sts)<br>-{<br>- static const char * const tco_sts_bits[] = {<br>+ static const char *const tco_sts_bits[] = {<br> [0] = "NMI2SMI",<br> [1] = "SW_TCO",<br> [2] = "TCO_INT",<br>@@ -262,20 +97,8 @@<br> [20] = "SMLINK_SLV"<br> };<br> <br>- if (!tco_sts)<br>- return 0;<br>-<br>- printk(BIOS_DEBUG, "TCO_STS: ");<br>- print_status_bits(tco_sts, tco_sts_bits);<br>- printk(BIOS_DEBUG, "\n");<br>-<br>- return tco_sts;<br>-}<br>-<br>-/* Print, clear, and return TCO status */<br>-u32 clear_tco_status(void)<br>-{<br>- return print_tco_status(reset_tco_status());<br>+ *a = ARRAY_SIZE(tco_sts_bits);<br>+ return tco_sts_bits;<br> }<br> <br> /* Enable TCO SCI */<br>@@ -285,106 +108,36 @@<br> outl(TCOSCI_STS, ACPI_BASE_ADDRESS + GPE0_STS(3));<br> <br> /* Enable TCO SCI events */<br>- enable_gpe(TCOSCI_EN);<br>+ pmc_enable_gpe(TCOSCI_EN);<br> }<br>-<br> <br> /*<br> * GPE0<br> */<br> <br>-/* Clear a GPE0 status and return events that are enabled and active */<br>-static u32 reset_gpe(u16 sts_reg, u16 en_reg)<br>+const char *const *soc_gpe_sts_array(int *a)<br> {<br>- u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg);<br>- u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg);<br>-<br>- outl(gpe0_sts, ACPI_BASE_ADDRESS + sts_reg);<br>-<br>- /* Only report enabled events */<br>- return gpe0_sts & gpe0_en;<br>-}<br>-<br>-/* Print GPE0 status bits */<br>-static u32 print_gpe_status(u32 gpe0_sts, const char * const bit_names[])<br>-{<br>- if (!gpe0_sts)<br>- return 0;<br>-<br>- printk(BIOS_DEBUG, "GPE0_STS: ");<br>- print_status_bits(gpe0_sts, bit_names);<br>- printk(BIOS_DEBUG, "\n");<br>-<br>- return gpe0_sts;<br>-}<br>-<br>-/* Print GPE0 GPIO status bits */<br>-static u32 print_gpe_gpio(u32 gpe0_sts, int start)<br>-{<br>- if (!gpe0_sts)<br>- return 0;<br>-<br>- printk(BIOS_DEBUG, "GPE0_STS: ");<br>- print_gpio_status(gpe0_sts, start);<br>- printk(BIOS_DEBUG, "\n");<br>-<br>- return gpe0_sts;<br>-}<br>-<br>-/* Clear all GPE status and return "standard" GPE event status */<br>-u32 clear_gpe_status(void)<br>-{<br>- static const char * const gpe0_sts_3_bits[] = {<br>- [1] = "HOTPLUG",<br>+ static const char *const gpe_sts_bits[] = {<br>+ [0] = "PCIE_SCI",<br> [2] = "SWGPE",<br>- [6] = "TCO_SCI",<br>- [7] = "SMB_WAK",<br>+ [3] = "PCIE_WAKE0",<br>+ [4] = "PUNIT",<br>+ [6] = "PCIE_WAKE1",<br>+ [7] = "PCIE_WAKE2",<br>+ [8] = "PCIE_WAKE3",<br> [9] = "PCI_EXP",<br> [10] = "BATLOW",<br>- [11] = "PME",<br>- [12] = "ME",<br>- [13] = "PME_B0",<br>- [14] = "eSPI",<br>- [15] = "GPIO Tier-2",<br>- [16] = "LAN_WAKE",<br>- [18] = "WADT"<br>+ [11] = "CSE_PME",<br>+ [12] = "XDCI_PME",<br>+ [13] = "XHCI_PME",<br>+ [14] = "AVS_PME",<br>+ [15] = "GPIO_TIER1_SCI",<br>+ [16] = "SMB_WAK",<br>+ [17] = "SATA_PME",<br> };<br> <br>- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);<br>- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);<br>- print_gpe_gpio(reset_gpe(GPE0_STS(GPE_95_64), GPE0_EN(GPE_95_64)), 64);<br>- return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),<br>- gpe0_sts_3_bits);<br>-}<br>-<br>-/* Read and clear GPE status (defined in arch/acpi.h) */<br>-int acpi_get_gpe(int gpe)<br>-{<br>- int bank;<br>- uint32_t mask, sts;<br>- struct stopwatch sw;<br>- int rc = 0;<br>-<br>- if (gpe < 0 || gpe > GPE0_WADT)<br>- return -1;<br>-<br>- bank = gpe / 32;<br>- mask = 1 << (gpe % 32);<br>-<br>- /* Wait up to 1ms for GPE status to clear */<br>- stopwatch_init_msecs_expire(&sw, 1);<br>- do {<br>- if (stopwatch_expired(&sw))<br>- return rc;<br>-<br>- sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));<br>- if (sts & mask) {<br>- outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));<br>- rc = 1;<br>- }<br>- } while (sts & mask);<br>-<br>- return rc;<br>+ *a = ARRAY_SIZE(gpe_sts_bits);<br>+ return gpe_sts_bits;<br> }<br> <br> /* Enable all requested GPE */<br>@@ -394,28 +147,6 @@<br> outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32));<br> outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_95_64));<br> outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));<br>-}<br>-<br>-/* Disable all GPE */<br>-void disable_all_gpe(void)<br>-{<br>- enable_all_gpe(0, 0, 0, 0);<br>-}<br>-<br>-/* Enable a standard GPE */<br>-void enable_gpe(u32 mask)<br>-{<br>- u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));<br>- gpe0_en |= mask;<br>- outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));<br>-}<br>-<br>-/* Disable a standard GPE */<br>-void disable_gpe(u32 mask)<br>-{<br>- u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));<br>- gpe0_en &= ~mask;<br>- outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));<br> }<br> <br> int acpi_sci_irq(void)<br>@@ -455,7 +186,12 @@<br> /* 4KiB alignment. */<br> reg32 &= ~0xfff;<br> <br>- return (void *)(uintptr_t)reg32;<br>+ return (void *)(uintptr_t) reg32;<br>+}<br>+<br>+uint16_t soc_tco_base(void)<br>+{<br>+ return (uintptr_t) (smbus_tco_regs());<br> }<br> <br> uint16_t smbus_tco_regs(void)<br>@@ -469,59 +205,50 @@<br> return reg16;<br> }<br> <br>-void poweroff(void)<br>+uint32_t soc_reset_tco(void)<br> {<br>- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));<br>+ u16 tco1_sts;<br>+ u16 tco2_sts;<br>+ u16 tcobase;<br> <br>- /*<br>- * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM<br>- * to transition to S5 state. If halt is called in SMM, then it prevents<br>- * the SMI handler from being triggered and system never enters S5.<br>- */<br>- if (!ENV_SMM)<br>- halt();<br>+ tcobase = smbus_tco_regs();<br>+<br>+ /* TCO Status 2 register */<br>+ tco2_sts = inw(tcobase + TCO2_STS);<br>+ tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);<br>+ outw(tco2_sts, tcobase + TCO2_STS);<br>+<br>+ /* TCO Status 1 register */<br>+ tco1_sts = inw(tcobase + TCO1_STS);<br>+<br>+ /* Clear SECOND_TO_STS bit */<br>+ if (tco2_sts & TCO2_STS_SECOND_TO)<br>+ outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);<br>+<br>+ return (tco2_sts << 16) | tco1_sts;<br> }<br> <br>-void pmc_gpe_init(void)<br>+uintptr_t soc_read_pmc_base(void)<br>+{<br>+ return (uintptr_t) (pmc_mmio_regs());<br>+}<br>+<br>+uint8_t soc_get_devicetree_info(int8_t *dw0, int8_t *dw1, int8_t *dw2)<br> {<br> DEVTREE_CONST struct soc_intel_skylake_config *config;<br>- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);<br>- uint8_t *pmc_regs;<br>- uint32_t gpio_cfg;<br>- uint32_t gpio_cfg_reg;<br>- const uint32_t gpio_cfg_mask =<br>- (GPE0_DWX_MASK << GPE0_DW0_SHIFT) |<br>- (GPE0_DWX_MASK << GPE0_DW1_SHIFT) |<br>- (GPE0_DWX_MASK << GPE0_DW2_SHIFT);<br> <br> /* Look up the device in devicetree */<br>+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);<br> if (!dev || !dev->chip_info) {<br> printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");<br>- return;<br>+ return -1;<br> }<br> config = dev->chip_info;<br>- pmc_regs = pmc_mmio_regs();<br> <br>- /* Route the GPIOs to the GPE0 block. Determine that all values<br>- * are different, and if they aren't use the reset values. */<br>- gpio_cfg = 0;<br>- if (config->gpe0_dw0 == config->gpe0_dw1 ||<br>- config->gpe0_dw1 == config->gpe0_dw2) {<br>- printk(BIOS_INFO, "PMC: Using default GPE route.\n");<br>- gpio_cfg = read32(pmc_regs + GPIO_CFG);<br>- } else {<br>- gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT;<br>- gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT;<br>- gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT;<br>- }<br>- gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask;<br>- gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;<br>- write32(pmc_regs + GPIO_CFG, gpio_cfg_reg);<br>+ /* Assign to out variable */<br>+ *dw0 = config->gpe0_dw0;<br>+ *dw1 = config->gpe0_dw1;<br>+ *dw2 = config->gpe0_dw2;<br> <br>- /* Set the routes in the GPIO communities as well. */<br>- gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT);<br>-<br>- /* Set GPE enables based on devictree. */<br>- enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,<br>- config->gpe0_en_3, config->gpe0_en_4);<br>+ return 0;<br> }<br>diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c<br>index 6910914..1fc76ac 100644<br>--- a/src/soc/intel/skylake/reset.c<br>+++ b/src/soc/intel/skylake/reset.c<br>@@ -32,9 +32,9 @@<br> * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]<br> */<br> pmc_regs = pmc_mmio_regs();<br>- reg32 = read32(pmc_regs + ETR3);<br>- reg32 |= ETR3_CF9GR;<br>- write32(pmc_regs + ETR3, reg32);<br>+ reg32 = read32(pmc_regs + ETR);<br>+ reg32 |= CF9_GLB_RST;<br>+ write32(pmc_regs + ETR, reg32);<br> <br> /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port<br> * to global reset platform */<br>diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c<br>index 61851a5..6cf2104 100644<br>--- a/src/soc/intel/skylake/romstage/power_state.c<br>+++ b/src/soc/intel/skylake/romstage/power_state.c<br>@@ -26,12 +26,12 @@<br> #include <stdlib.h><br> #include <string.h><br> #include <soc/iomap.h><br>-#include <soc/pmc.h><br> #include <soc/smbus.h><br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br> #include <soc/romstage.h><br> #include <vboot/vboot_common.h><br>+#include <intelblocks/pmclib.h><br> <br> static struct chipset_power_state power_state CAR_GLOBAL;<br> <br>@@ -49,42 +49,28 @@<br> }<br> memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));<br> }<br>+<br> ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)<br> <br> /* Return 0, 3, or 5 to indicate the previous sleep state. */<br>-static uint32_t prev_sleep_state(struct chipset_power_state *ps)<br>+void chipset_prev_sleep_state(struct chipset_power_state *ps,<br>+ int *prev_sleep_state)<br> {<br>- /* Default to S0. */<br>- uint32_t prev_sleep_state = ACPI_S0;<br> <br>- if (ps->pm1_sts & WAK_STS) {<br>- switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {<br>- case ACPI_S3:<br>- if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))<br>- prev_sleep_state = ACPI_S3;<br>- break;<br>- case ACPI_S5:<br>- prev_sleep_state = ACPI_S5;<br>- break;<br>- }<br>- /* Clear SLP_TYP. */<br>- outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);<br>- } else {<br>- /*<br>- * Check for any power failure to determine if this a wake from<br>- * S5 because the PCH does not set the WAK_STS bit when waking<br>- * from a true G3 state.<br>- */<br>- if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))<br>- prev_sleep_state = ACPI_S5;<br>- }<br>+ /*<br>+ * Check for any power failure to determine if this a wake from<br>+ * S5 because the PCH does not set the WAK_STS bit when waking<br>+ * from a true G3 state.<br>+ */<br>+ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))<br>+ *prev_sleep_state = ACPI_S5;<br> <br> /*<br> * If waking from S3 determine if deep S3 is enabled. If not,<br> * need to check both deep sleep well and normal suspend well.<br> * Otherwise just check deep sleep well.<br> */<br>- if (prev_sleep_state == ACPI_S3) {<br>+ if (*prev_sleep_state == ACPI_S3) {<br> /* PWR_FLR represents deep sleep power well loss. */<br> uint32_t mask = PWR_FLR;<br> <br>@@ -93,59 +79,27 @@<br> mask |= SUS_PWR_FLR;<br> <br> if (ps->gen_pmcon_b & mask)<br>- prev_sleep_state = ACPI_S5;<br>+ *prev_sleep_state = ACPI_S5;<br> }<br>-<br>- return prev_sleep_state;<br> }<br> <br>-static void dump_power_state(struct chipset_power_state *ps)<br>-{<br>- printk(BIOS_DEBUG, "PM1_STS: %04x\n", ps->pm1_sts);<br>- printk(BIOS_DEBUG, "PM1_EN: %04x\n", ps->pm1_en);<br>- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", ps->pm1_cnt);<br>- printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",<br>- ps->tco1_sts, ps->tco2_sts);<br>-<br>- printk(BIOS_DEBUG, "GPE0_STS: %08x %08x %08x %08x\n",<br>- ps->gpe0_sts[0], ps->gpe0_sts[1],<br>- ps->gpe0_sts[2], ps->gpe0_sts[3]);<br>- printk(BIOS_DEBUG, "GPE0_EN: %08x %08x %08x %08x\n",<br>- ps->gpe0_en[0], ps->gpe0_en[1],<br>- ps->gpe0_en[2], ps->gpe0_en[3]);<br>-<br>- printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",<br>- ps->gen_pmcon_a, ps->gen_pmcon_b);<br>-<br>- printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",<br>- ps->gblrst_cause[0], ps->gblrst_cause[1]);<br>-<br>- printk(BIOS_DEBUG, "Previous Sleep State: S%d\n",<br>- ps->prev_sleep_state);<br>-}<br>-<br>-/* Fill power state structure from ACPI PM registers */<br>-struct chipset_power_state *fill_power_state(void)<br>+int soc_fill_power_state(void)<br> {<br> uint16_t tcobase;<br> uint8_t *pmc;<br>- struct chipset_power_state *ps = car_get_var_ptr(&power_state);<br>+ struct chipset_power_state *ps;<br>+<br>+ ps = car_get_var_ptr(&power_state);<br>+<br>+ pmc_fill_power_state(ps);<br> <br> tcobase = smbus_tco_regs();<br> <br>- ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);<br>- ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);<br>- ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);<br> ps->tco1_sts = inw(tcobase + TCO1_STS);<br> ps->tco2_sts = inw(tcobase + TCO2_STS);<br>- ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));<br>- ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));<br>- ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));<br>- ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));<br>- ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));<br>- ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));<br>- ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));<br>- ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));<br>+<br>+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",<br>+ ps->tco1_sts, ps->tco2_sts);<br> <br> ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);<br> ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);<br>@@ -154,28 +108,11 @@<br> ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);<br> ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);<br> <br>- ps->prev_sleep_state = prev_sleep_state(ps);<br>+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",<br>+ ps->gen_pmcon_a, ps->gen_pmcon_b);<br> <br>- dump_power_state(ps);<br>+ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",<br>+ ps->gblrst_cause[0], ps->gblrst_cause[1]);<br> <br>- return ps;<br>-}<br>-<br>-int vboot_platform_is_resuming(void)<br>-{<br>- return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;<br>-}<br>-<br>-/*<br>- * The PM1 control is set to S5 when vboot requests a reboot because the power<br>- * state code above may not have collected it's data yet. Therefore, set it to<br>- * S5 when vboot requests a reboot. That's necessary if vboot fails in the<br>- * resume path and requests a reboot. This prevents a reboot loop where the<br>- * error is continually hit on the failing vboot resume path.<br>- */<br>-void vboot_platform_prepare_reboot(void)<br>-{<br>- uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;<br>-<br>- outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);<br>+ return ps->prev_sleep_state;<br> }<br>diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c<br>index cb704fd..e2e3921 100644<br>--- a/src/soc/intel/skylake/romstage/romstage.c<br>+++ b/src/soc/intel/skylake/romstage/romstage.c<br>@@ -34,7 +34,6 @@<br> #include <soc/pci_devs.h><br> #include <soc/pei_wrapper.h><br> #include <soc/pm.h><br>-#include <soc/pmc.h><br> #include <soc/serialio.h><br> #include <soc/romstage.h><br> #include <stage_cache.h><br>diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>index 4530190..69a0934 100644<br>--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>@@ -120,16 +120,14 @@<br> bool s3wake;<br> struct postcar_frame pcf;<br> uintptr_t top_of_ram;<br>- struct chipset_power_state *ps;<br>+ //struct chipset_power_state *ps;<br> <br> console_init();<br> <br> /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */<br> systemagent_early_init();<br>-<br>- ps = fill_power_state();<br> timestamp_add_now(TS_START_ROMSTAGE);<br>- s3wake = ps->prev_sleep_state == ACPI_S3;<br>+ s3wake = soc_fill_power_state() == ACPI_S3;<br> fsp_memory_init(s3wake);<br> pmc_set_disb();<br> if (!s3wake)<br>diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c<br>index 7343637..7315a76 100644<br>--- a/src/soc/intel/skylake/smi.c<br>+++ b/src/soc/intel/skylake/smi.c<br>@@ -27,6 +27,7 @@<br> #include <soc/pch.h><br> #include <soc/pm.h><br> #include <soc/smm.h><br>+#include <intelblocks/pmclib.h><br> <br> void southbridge_smm_clear_state(void)<br> {<br>@@ -44,18 +45,18 @@<br> printk(BIOS_DEBUG, "\n");<br> <br> /* Dump and clear status registers */<br>- clear_smi_status();<br>- clear_pm1_status();<br>- clear_tco_status();<br>- clear_gpe_status();<br>+ pmc_clear_smi_status();<br>+ pmc_clear_pm1_status();<br>+ pmc_clear_tco_status();<br>+ pmc_clear_gpe_status();<br> }<br> <br> void southbridge_smm_enable_smi(void)<br> {<br> printk(BIOS_DEBUG, "Enabling SMIs.\n");<br> /* Configure events */<br>- enable_pm1(PWRBTN_EN | GBL_EN);<br>- disable_gpe(PME_B0_EN);<br>+ pmc_enable_pm1(PWRBTN_EN | GBL_EN);<br>+ pmc_disable_gpe(PME_B0_EN);<br> <br> /*<br> * Enable SMI generation:<br>@@ -67,7 +68,7 @@<br> * - on microcontroller writes (io 0x62/0x66)<br> * - on TCO events<br> */<br>- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);<br>+ pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);<br> }<br> <br> void smm_setup_structures(void *gnvs, void *tcg, void *smi1)<br>diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c<br>index c4c4a7b..2d20cc0 100644<br>--- a/src/soc/intel/skylake/smihandler.c<br>+++ b/src/soc/intel/skylake/smihandler.c<br>@@ -24,6 +24,7 @@<br> #include <elog.h><br> #include <intelblocks/fast_spi.h><br> #include <intelblocks/pcr.h><br>+#include <intelblocks/pmclib.h><br> #include <delay.h><br> #include <device/pci_def.h><br> #include <elog.h><br>@@ -36,7 +37,6 @@<br> #include <soc/pch.h><br> #include <soc/pcr_ids.h><br> #include <soc/pm.h><br>-#include <soc/pmc.h><br> #include <soc/smm.h><br> #include <types.h><br> <br>@@ -81,7 +81,7 @@<br> /* Set the EOS bit */<br> void southbridge_smi_set_eos(void)<br> {<br>- enable_smi(EOS);<br>+ pmc_enable_smi(EOS);<br> }<br> <br> static void busmaster_disable_on_bus(int bus)<br>@@ -136,7 +136,7 @@<br> outb(tmp72, 0x72);<br> <br> /* First, disable further SMIs */<br>- disable_smi(SLP_SMI_EN);<br>+ pmc_disable_smi(SLP_SMI_EN);<br> <br> /* Figure out SLP_TYP */<br> reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);<br>@@ -152,7 +152,7 @@<br> elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br> <br> /* Clear pending GPE events */<br>- clear_gpe_status();<br>+ pmc_clear_gpe_status();<br> <br> /* Next, do the deed. */<br> switch (slp_typ) {<br>@@ -173,7 +173,7 @@<br> /*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/<br> s5pwr = MAINBOARD_POWER_ON;<br> /* Disable all GPE */<br>- disable_all_gpe();<br>+ pmc_disable_all_gpe();<br> <br> /*<br> * Always set the flag in case CMOS was changed on runtime. For<br>@@ -199,7 +199,7 @@<br> * event again. We need to set BIT13 (SLP_EN) though to make the<br> * sleep happen.<br> */<br>- enable_pm1_control(SLP_EN);<br>+ pmc_enable_pm1_control(SLP_EN);<br> <br> /* Make sure to stop executing code here for S3/S4/S5 */<br> if (slp_typ >= ACPI_S3)<br>@@ -213,7 +213,7 @@<br> reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);<br> if (reg32 & SCI_EN) {<br> /* The OS is not an ACPI OS, so we set the state to S0 */<br>- disable_pm1_control(SLP_EN | SLP_TYP);<br>+ pmc_disable_pm1_control(SLP_EN | SLP_TYP);<br> }<br> }<br> <br>@@ -304,11 +304,11 @@<br> printk(BIOS_DEBUG, "P-state control\n");<br> break;<br> case APM_CNT_ACPI_DISABLE:<br>- disable_pm1_control(SCI_EN);<br>+ pmc_disable_pm1_control(SCI_EN);<br> printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");<br> break;<br> case APM_CNT_ACPI_ENABLE:<br>- enable_pm1_control(SCI_EN);<br>+ pmc_enable_pm1_control(SCI_EN);<br> printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");<br> break;<br> case APM_CNT_FINALIZE:<br>@@ -339,7 +339,7 @@<br> <br> static void southbridge_smi_pm1(void)<br> {<br>- u16 pm1_sts = clear_pm1_status();<br>+ u16 pm1_sts = pmc_clear_pm1_status();<br> <br> /*<br> * While OSPM is not active, poweroff immediately on a power button<br>@@ -349,14 +349,14 @@<br> /* power button pressed */<br> if (IS_ENABLED(CONFIG_ELOG_GSMI))<br> elog_add_event(ELOG_TYPE_POWER_BUTTON);<br>- disable_pm1_control(-1UL);<br>- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));<br>+ pmc_disable_pm1_control(-1UL);<br>+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));<br> }<br> }<br> <br> static void southbridge_smi_gpe0(void)<br> {<br>- clear_gpe_status();<br>+ pmc_clear_gpe_status();<br> }<br> <br> void __attribute__((weak))<br>@@ -392,7 +392,7 @@<br> <br> static void southbridge_smi_tco(void)<br> {<br>- u32 tco_sts = clear_tco_status();<br>+ u32 tco_sts = pmc_clear_tco_status();<br> <br> /* Any TCO event? */<br> if (!tco_sts)<br>@@ -520,7 +520,7 @@<br> * We need to clear the SMI status registers, or we won't see what's<br> * happening in the following calls.<br> */<br>- smi_sts = clear_smi_status();<br>+ smi_sts = pmc_clear_smi_status();<br> <br> /* Call SMI sub handler for each of the status bits */<br> for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20219">change 20219</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If7be9860bdd7d825bb7302168501129f09ca4741 </div>
<div style="display:none"> Gerrit-Change-Number: 20219 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shaunak Saha <shaunak.saha@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Andrey Petrov <andrey.petrov@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>