[coreboot-gerrit] Change in coreboot[master]: southbridge/intel/lynxpoint: Fix undefined behavior.

[Ryan Salsamendi (Code Review)]

Ryan Salsamendi has uploaded this change for review. ( https://review.coreboot.org/20443


Change subject: southbridge/intel/lynxpoint: Fix undefined behavior.
......................................................................

southbridge/intel/lynxpoint: Fix undefined behavior.

Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.

Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266
Signed-off-by: Ryan Salsamendi <rsalsamendi at hotmail.com>
---
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/pmutil.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
7 files changed, 11 insertions(+), 11 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20443/1

diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index 35dc63c..0b1acdd 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -48,7 +48,7 @@
 	u16 reg16;
 	u32 reg32;
 
-	if (RCBA32(0x2030) & (1 << 31)) {
+	if (RCBA32(0x2030) & (1UL << 31)) {
 		reg32 = pci_read_config32(dev, 0x120);
 		reg32 &= 0xf8ffff01;
 		reg32 |= (1 << 25);
@@ -72,9 +72,9 @@
 						(1 << 25) | (1 << 26))) {
 		reg32 = pci_read_config32(dev, 0x120);
 		if (pch_is_lp())
-			reg32 &= ~(1 << 31);
+			reg32 &= ~(1UL << 31);
 		else
-			reg32 |= (1 << 31);
+			reg32 |= (1UL << 31);
 		pci_write_config32(dev, 0x120, reg32);
 	}
 
@@ -101,7 +101,7 @@
 
 	if (!pch_is_lp()) {
 		reg32 = pci_read_config32(dev, 0xd0);
-		reg32 &= ~(1 << 31);
+		reg32 &= ~(1UL << 31);
 		pci_write_config32(dev, 0xd0, reg32);
 	}
 
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index d295c88..6c4acd8 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -429,7 +429,7 @@
 
 	reg32 = RCBA32(CG);
 	reg32 |= (1 << 22); // HDA Dynamic
-	reg32 |= (1 << 31); // LPC Dynamic
+	reg32 |= (1UL << 31); // LPC Dynamic
 	reg32 |= (1 << 16); // PCIe Dynamic
 	reg32 |= (1 << 27); // HPET Dynamic
 	reg32 |= (1 << 28); // GPIO Dynamic
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 8cae50a..d76faf7 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -547,7 +547,7 @@
 #define RPFN		0x0404	/* 32bit */
 
 /* Root Port configuratinon space hide */
-#define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
+#define RPFN_HIDE(port)         (1UL << (((port) * 4) + 3))
 /* Get the function number assigned to a Root Port */
 #define RPFN_FNGET(reg,port)    (((reg) >> ((port) * 4)) & 7)
 /* Set the function number for a Root Port */
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 3fd8d1e..3d01cd6 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -608,7 +608,7 @@
 	pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11));
 	pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
 
-	pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
+	pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16));
 
 	/* Set L1 exit latency in LCAP register. */
 	if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 90045d1..d895c56 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -45,7 +45,7 @@
 		return;
 
 	for (i=31; i>=0; i--) {
-		if (status & (1 << i)) {
+		if (status & (1UL << i)) {
 			if (bit_names[i])
 				printk(BIOS_DEBUG, "%s ", bit_names[i]);
 			else
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 98cd0bc..31081d7 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -297,7 +297,7 @@
 
 	reg32 = pci_read_config32(dev, 0x300);
 	reg32 |= (1 << 17) | (1 << 16);
-	reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
+	reg32 |= (1UL << 31) | (1 << 30) | (1 << 29);
 	pci_write_config32(dev, 0x300, reg32);
 }
 
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 0acf35f..28e6521 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -342,13 +342,13 @@
 
 	/* D20:F0:44h[31] = 1 (Access Control Bit) */
 	reg32 = pci_read_config32(dev, 0x44);
-	reg32 |= (1 << 31);
+	reg32 |= (1UL << 31);
 	pci_write_config32(dev, 0x44, reg32);
 
 	/* D20:F0:40h[31,23] = 10b (OC Configuration Done) */
 	reg32 = pci_read_config32(dev, 0x40);
 	reg32 &= ~(1 << 23); /* unsupported request */
-	reg32 |= (1 << 31);
+	reg32 |= (1UL << 31);
 	pci_write_config32(dev, 0x40, reg32);
 
 	if (acpi_is_wakeup_s3()) {

-- 
To view, visit https://review.coreboot.org/20443
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266
Gerrit-Change-Number: 20443
Gerrit-PatchSet: 1
Gerrit-Owner: Ryan Salsamendi <rsalsamendi at hotmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170701/d0709324/attachment-0001.html>