<p>Ryan Salsamendi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20443">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">southbridge/intel/lynxpoint: Fix undefined behavior.<br><br>Fix reports found by undefined behavior sanitizer. Left shifting an int<br>where the right operand is >= the width of the type is undefined. Add<br>UL suffix since it's safe for unsigned types.<br><br>Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266<br>Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com><br>---<br>M src/southbridge/intel/lynxpoint/azalia.c<br>M src/southbridge/intel/lynxpoint/lpc.c<br>M src/southbridge/intel/lynxpoint/pch.h<br>M src/southbridge/intel/lynxpoint/pcie.c<br>M src/southbridge/intel/lynxpoint/pmutil.c<br>M src/southbridge/intel/lynxpoint/sata.c<br>M src/southbridge/intel/lynxpoint/usb_xhci.c<br>7 files changed, 11 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20443/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c<br>index 35dc63c..0b1acdd 100644<br>--- a/src/southbridge/intel/lynxpoint/azalia.c<br>+++ b/src/southbridge/intel/lynxpoint/azalia.c<br>@@ -48,7 +48,7 @@<br> u16 reg16;<br> u32 reg32;<br> <br>- if (RCBA32(0x2030) & (1 << 31)) {<br>+ if (RCBA32(0x2030) & (1UL << 31)) {<br> reg32 = pci_read_config32(dev, 0x120);<br> reg32 &= 0xf8ffff01;<br> reg32 |= (1 << 25);<br>@@ -72,9 +72,9 @@<br> (1 << 25) | (1 << 26))) {<br> reg32 = pci_read_config32(dev, 0x120);<br> if (pch_is_lp())<br>- reg32 &= ~(1 << 31);<br>+ reg32 &= ~(1UL << 31);<br> else<br>- reg32 |= (1 << 31);<br>+ reg32 |= (1UL << 31);<br> pci_write_config32(dev, 0x120, reg32);<br> }<br> <br>@@ -101,7 +101,7 @@<br> <br> if (!pch_is_lp()) {<br> reg32 = pci_read_config32(dev, 0xd0);<br>- reg32 &= ~(1 << 31);<br>+ reg32 &= ~(1UL << 31);<br> pci_write_config32(dev, 0xd0, reg32);<br> }<br> <br>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c<br>index d295c88..6c4acd8 100644<br>--- a/src/southbridge/intel/lynxpoint/lpc.c<br>+++ b/src/southbridge/intel/lynxpoint/lpc.c<br>@@ -429,7 +429,7 @@<br> <br> reg32 = RCBA32(CG);<br> reg32 |= (1 << 22); // HDA Dynamic<br>- reg32 |= (1 << 31); // LPC Dynamic<br>+ reg32 |= (1UL << 31); // LPC Dynamic<br> reg32 |= (1 << 16); // PCIe Dynamic<br> reg32 |= (1 << 27); // HPET Dynamic<br> reg32 |= (1 << 28); // GPIO Dynamic<br>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h<br>index 8cae50a..d76faf7 100644<br>--- a/src/southbridge/intel/lynxpoint/pch.h<br>+++ b/src/southbridge/intel/lynxpoint/pch.h<br>@@ -547,7 +547,7 @@<br> #define RPFN 0x0404 /* 32bit */<br> <br> /* Root Port configuratinon space hide */<br>-#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))<br>+#define RPFN_HIDE(port) (1UL << (((port) * 4) + 3))<br> /* Get the function number assigned to a Root Port */<br> #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)<br> /* Set the function number for a Root Port */<br>diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c<br>index 3fd8d1e..3d01cd6 100644<br>--- a/src/southbridge/intel/lynxpoint/pcie.c<br>+++ b/src/southbridge/intel/lynxpoint/pcie.c<br>@@ -608,7 +608,7 @@<br> pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11));<br> pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));<br> <br>- pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));<br>+ pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16));<br> <br> /* Set L1 exit latency in LCAP register. */<br> if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))<br>diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c<br>index 90045d1..d895c56 100644<br>--- a/src/southbridge/intel/lynxpoint/pmutil.c<br>+++ b/src/southbridge/intel/lynxpoint/pmutil.c<br>@@ -45,7 +45,7 @@<br> return;<br> <br> for (i=31; i>=0; i--) {<br>- if (status & (1 << i)) {<br>+ if (status & (1UL << i)) {<br> if (bit_names[i])<br> printk(BIOS_DEBUG, "%s ", bit_names[i]);<br> else<br>diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c<br>index 98cd0bc..31081d7 100644<br>--- a/src/southbridge/intel/lynxpoint/sata.c<br>+++ b/src/southbridge/intel/lynxpoint/sata.c<br>@@ -297,7 +297,7 @@<br> <br> reg32 = pci_read_config32(dev, 0x300);<br> reg32 |= (1 << 17) | (1 << 16);<br>- reg32 |= (1 << 31) | (1 << 30) | (1 << 29);<br>+ reg32 |= (1UL << 31) | (1 << 30) | (1 << 29);<br> pci_write_config32(dev, 0x300, reg32);<br> }<br> <br>diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c<br>index 0acf35f..28e6521 100644<br>--- a/src/southbridge/intel/lynxpoint/usb_xhci.c<br>+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c<br>@@ -342,13 +342,13 @@<br> <br> /* D20:F0:44h[31] = 1 (Access Control Bit) */<br> reg32 = pci_read_config32(dev, 0x44);<br>- reg32 |= (1 << 31);<br>+ reg32 |= (1UL << 31);<br> pci_write_config32(dev, 0x44, reg32);<br> <br> /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */<br> reg32 = pci_read_config32(dev, 0x40);<br> reg32 &= ~(1 << 23); /* unsupported request */<br>- reg32 |= (1 << 31);<br>+ reg32 |= (1UL << 31);<br> pci_write_config32(dev, 0x40, reg32);<br> <br> if (acpi_is_wakeup_s3()) {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20443">change 20443</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20443"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266 </div>
<div style="display:none"> Gerrit-Change-Number: 20443 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ryan Salsamendi <rsalsamendi@hotmail.com> </div>