[coreboot-gerrit] New patch to review for coreboot: mainboard/intel/kblrvp: Enable Audio for RVP3

[Rizwan Qureshi (rizwan.qureshi@intel.com)]

Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18219

-gerrit

commit d506ef40f468c0f38450a1a96c9db0b2904e255c
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Tue Jan 24 14:06:04 2017 +0530

    mainboard/intel/kblrvp: Enable Audio for RVP3
    
    Maxim 98927 and Realtek 5663 codecs have been hooked up to RVP3.
    Enable the required I2C devices and select appropriate config options
    for enabling audio feature on RVP3.
    
    BUG=None
    BRANCH=None
    TEST=with the required kernel driver support verfied audio playback
    on headset and speaker.
    
    Change-Id: I03cf1ae1a6106be13503e3f13bac05194a25c606
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: M Naveen <naveen.m at intel.com>
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
 src/mainboard/intel/kblrvp/Kconfig                 |  3 +-
 .../intel/kblrvp/variants/rvp3/devicetree.cb       | 32 +++++++++++++++++++++-
 .../kblrvp/variants/rvp3/include/variant/gpio.h    |  2 +-
 3 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index f68d8ca..83f4763 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -13,7 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MAINBOARD_USES_FSP2_0
 	select MAINBOARD_HAS_CHROMEOS
 	select GENERIC_SPD_BIN
-
+	select DRIVERS_I2C_RT5663 if BOARD_INTEL_KBLRVP3
+	select DRIVERS_I2C_MAX98927 if BOARD_INTEL_KBLRVP3
 config CHROMEOS
 	select LID_SWITCH
 
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
index c2dde4f..7142373 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
@@ -23,6 +23,9 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# FSP Configuration
+	register "EnableAzalia" = "1"
+	register "DspEnable" = "1"
+	register "IoBufferOwnership" = "3"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
@@ -220,7 +223,34 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
-		device pci 15.0 on  end # I2C #0
+		device pci 15.0 on
+			chip drivers/i2c/max98927
+				register "interleave_mode" = "1"
+				register "reg" = "0x3A"
+				register "sub_reg" = "0x39"
+				register "regcfg" = "{
+					0, 0x1c, 0xfe,
+					0, 0x1e, 0x00,
+					0, 0x24, 0x85,
+					0, 0x25, 0x85,
+					0, 0x36, 0x03,
+					0, 0x37, 0x03,
+					0, 0x3C, 0x05,
+					1, 0x1c, 0xfd,
+					1, 0x1e, 0x11,
+					1, 0x24, 0x85,
+					1, 0x25, 0x40,
+					1, 0x36, 0x38,
+					1, 0x37, 0x03,
+					1, 0x3C, 0x05
+				}"
+				device i2c 3A on end
+			end
+			chip drivers/i2c/rt5663
+				register "irq" = "IRQ_LEVEL_LOW(GPP_E22_IRQ)"
+				device i2c 13 on end
+			end
+		end # I2C #0
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
index c6f4123..bebda7c 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
@@ -159,7 +159,7 @@ static const struct pad_config gpio_table[] = {
 /* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
 /* DDPC_CTRLCLK */	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 /* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
-/* DDPD_CTRLCLK */	PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
+/* DDPD_CTRLCLK */	PAD_CFG_GPI_APIC(GPP_E22, NONE, PLTRST),
 /* TCH_PNL_RST */	PAD_CFG_GPO(GPP_E23, 1, DEEP),
 /* I2S2_SCLK */		PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 /* I2S2_SFRM */		PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),