[coreboot-gerrit] New patch to review for coreboot: riscv: fix up issues related to M-mode misalign traps

[Ronald G. Minnich (rminnich@gmail.com)]

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18139

-gerrit

commit ee7d3b858c50b4c930250c1442759003947c1267
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Fri Jan 13 18:27:34 2017 -0800

    riscv: fix up issues related to M-mode misalign traps
    
    First, make sure that the lb_record allocator allocates
    128-bit-aligned pointers. This ensures safety up to rv128.
    
    Second, if we take an interrupt in M-mode, panic. We have
    no plans to support that. If you have alignment issues
    in M-mode it's a sign you need to fix your firmware.
    
    This gets me back up to a shell prompt on harvey, where
    before we would fail with an alignment trap in
    coreboot.
    
    Change-Id: Id683fe2baa8cbea9abfccab72cf66a44fc04429e
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/arch/riscv/trap_handler.c | 6 ++++++
 src/lib/coreboot_table.c      | 8 ++++++++
 2 files changed, 14 insertions(+)

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 9a8947c..272622c 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -150,6 +150,12 @@ static void interrupt_handler(trapframe *tf)
 {
 	uint64_t cause = tf->cause & ~0x8000000000000000ULL;
 	uint32_t msip, ssie;
+	bool mprv = !!(tf->status & MSTATUS_MPRV);
+
+	if (mprv) {
+		print_trap_information(tf);
+		die("Interrupt in M-mode. Fix your firmware");
+	}
 
 	switch (cause) {
 	case IRQ_M_TIMER:
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index f8da658..dadedc8 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -88,6 +88,14 @@ struct lb_record *lb_new_record(struct lb_header *header)
 	rec = lb_last_record(header);
 	if (header->table_entries) {
 		header->table_bytes += rec->size;
+		// If the rec->size is not aligned to something reasonable,
+		// some architectures can take alignment traps.
+		// Round up table_bytes to something that is future-proof,
+		// namely 128 bits (16 bytes). This will ensure that even
+		// the 128-bit RISCV won't get traps.
+		// We have roundup macros all over the tree; we need to
+		// clean that up at some point.
+		header->table_bytes = (header->table_bytes + 15) & ~0xf;
 	}
 	rec = lb_last_record(header);
 	header->table_entries++;