[coreboot-gerrit] New patch to review for coreboot: amd/mct/ddr3: Avoid using uninitialized register address in ECC setup

Timothy Pearson (tpearson@raptorengineering.com) gerrit at coreboot.org
Tue Jan 10 00:57:10 CET 2017


Timothy Pearson (tpearson at raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18079

-gerrit

commit ce7eb4853778c01ed9299b59953dcb8df9c89bf3
Author: Timothy Pearson <tpearson at raptorengineering.com>
Date:   Mon Jan 9 17:54:35 2017 -0600

    amd/mct/ddr3: Avoid using uninitialized register address in ECC setup
    
    Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as
    a register address under certain conditions.  Refactor mct_EnableDimmEccEn_D
    to use the explicit address of the register in all cases.
    
    Found-by: Coverity Scan #1347337
    Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8
    Signed-off-by: Timothy Pearson <tpearson at raptorengineering.com>
---
 src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 123b839..a292f39 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -2242,23 +2242,20 @@ void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u8 _DisableDramECC)
 {
 	u32 val;
-	u32 reg;
 	u32 dev;
 
 	/* Enable ECC correction if it was previously disabled */
-
 	dev = pDCTstat->dev_dct;
 
 	if ((_DisableDramECC & 0x01) == 0x01) {
-		reg = 0x90;
-		val = Get_NB32_DCT(dev, 0, reg);
+		val = Get_NB32_DCT(dev, 0, 0x90);
 		val |= (1<<DimmEcEn);
-		Set_NB32_DCT(dev, 0, reg, val);
+		Set_NB32_DCT(dev, 0, 0x90, val);
 	}
 	if ((_DisableDramECC & 0x02) == 0x02) {
-		val = Get_NB32_DCT(dev, 1, reg);
+		val = Get_NB32_DCT(dev, 1, 0x90);
 		val |= (1<<DimmEcEn);
-		Set_NB32_DCT(dev, 1, reg, val);
+		Set_NB32_DCT(dev, 1, 0x90, val);
 	}
 }
 



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