[coreboot-gerrit] New patch to review for coreboot: amd/mct/ddr3: Correctly program maximum read latency
Timothy Pearson (tpearson@raptorengineering.com)
gerrit at coreboot.org
Mon Jan 9 21:21:55 CET 2017
Timothy Pearson (tpearson at raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18072
-gerrit
commit b2506e740078661a54e78ccd6f8820dc65d75f90
Author: Timothy Pearson <tpearson at raptorengineering.com>
Date: Mon Jan 9 14:19:37 2017 -0600
amd/mct/ddr3: Correctly program maximum read latency
The existing code inadvertently calculated the maximum read
latency for nonexistent channel 2 instead of for channels
0 and 1 as intended. Fix the calls to the maximum read latency
training function.
Found-by: Coverity Scan #1347354
Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471
Signed-off-by: Timothy Pearson <tpearson at raptorengineering.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index fd8a8e7..984f604 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -1484,8 +1484,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
}
}
- /* Calculate and program MaxRdLatency */
- Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 0);
+ /* Calculate and program MaxRdLatency for both channels */
+ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 0, 0);
+ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 1, 0);
if (_DisableDramECC) {
mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);
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