[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Disable s0ix if not enabled in devicetree

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 25c7d9342b8bdee61710a516440e4b9c4b83fb09
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Feb 17 17:16:43 2017 -0800

    soc/intel/skylake: Disable s0ix if not enabled in devicetree
    
    There is an enable_s0ix config option in the devicetree that should
    be used to disable it when not set:
    
    - do not export C8/C9/C10 C-states in _CST
    - do not enable SLP_S0 in FSP
    
    BUG=chrome-os-partner:58666
    TEST=test on eve board to ensure that OS only sees 3 ACPI C-states
    instead of 6 and that it no longer attempts to enter C10
    
    Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/18394
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan at google.com>


See https://review.coreboot.org/18394 for details.

-gerrit