[coreboot-gerrit] New patch to review for coreboot: google/eve: Set rise/fall timing values for I2C bus 1

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18396

-gerrit

commit a43cdf2c0b571f25d56a8b490bf588c9910d13ec
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Feb 17 17:26:04 2017 -0800

    google/eve: Set rise/fall timing values for I2C bus 1
    
    Apply the measured rise and fall times for I2C bus 1 on Eve
    so it can be tuned properly for 400KHz operation.
    
    BUG=chrome-os-partner:63020
    TEST=verify I2C1 bus speed with a scope
    
    Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/eve/devicetree.cb | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index dfe7281..c600b5f 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -168,8 +168,12 @@ chip soc/intel/skylake
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"	# Audio
 
 	# Enable I2C1 bus early for TPM access
-	register "i2c[1].early_init" = "1"
-	register "i2c[1].speed" = "I2C_SPEED_FAST"
+	register "i2c[1]" = "{
+		.early_init = 1,
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 88,
+		.fall_time_ns = 32,
+	}"
 
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{