[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 17335fab175ed1a16f61729b03c1fbeeec366f37
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Sat Jan 14 06:08:21 2017 +0530

    soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support
    
    Add APIs and required parameters for creating Maxim 98927
    and Realtek 5336 SSP endpoints in NHLT table.
    
    BUG=chrome-os-partner:62051
    BRANCH=None
    TEST=check that NHLT table created is created properly
    
    Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
    Signed-off-by: M Naveen <naveen.m at intel.com>
    Reviewed-on: https://review.coreboot.org/18213
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan at google.com>


See https://review.coreboot.org/18213 for details.

-gerrit