[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/eve: Generate FPC device using SPI SSDT generator
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Mon Feb 13 01:30:22 CET 2017
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18343
-gerrit
commit b1758831c88f3fe80eb011839e49e24785ad07e8
Author: Furquan Shaikh <furquan at chromium.org>
Date: Sat Feb 11 12:02:40 2017 -0800
mainboard/google/eve: Generate FPC device using SPI SSDT generator
Use the newly added SPI SSDT generator for adding FPC device.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
src/mainboard/google/eve/Kconfig | 1 +
src/mainboard/google/eve/acpi/mainboard.asl | 49 -----------------------------
src/mainboard/google/eve/devicetree.cb | 11 ++++++-
src/mainboard/google/eve/dsdt.asl | 3 --
4 files changed, 11 insertions(+), 53 deletions(-)
diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index e83e7d9..1a4a4c5 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ID_AUTO
select BOARD_ROMSIZE_KB_16384
+ select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/eve/acpi/mainboard.asl b/src/mainboard/google/eve/acpi/mainboard.asl
deleted file mode 100644
index a55308f..0000000
--- a/src/mainboard/google/eve/acpi/mainboard.asl
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Scope (\_SB.PCI0.SPI1)
-{
- Device (FPC)
- {
- Name (_HID, "PRP0001")
- Name (_UID, 1)
- Name (_CRS, ResourceTemplate ()
- {
- SpiSerialBus (
- 0, // DeviceSelection (CS0)
- PolarityLow, // DeviceSelectionPolarity
- FourWireMode, // WireMode
- 8, // DataBitLength
- ControllerInitiated, // SlaveMode
- 1000000, // ConnectionSpeed (1MHz)
- ClockPolarityLow, // ClockPolarity
- ClockPhaseFirst, // ClockPhase
- "\\_SB.PCI0.SPI1", // ResourceSource
- 0, // ResourceSourceIndex
- ResourceConsumer, // ResourceUsage
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 }
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {
- "compatible",
- Package () { "fpc,fpc1020" }
- },
- }
- })
- }
-}
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index d619d60..c8d8175 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -256,7 +256,16 @@ chip soc/intel/skylake
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on end # GSPI #0
- device pci 1e.3 on end # GSPI #1
+ device pci 1e.3 on
+ chip drivers/spi/acpi
+ register "hid" = ""PRP0001""
+ register "uid" = "1"
+ register "speed" = "1000000"
+ register "compat_string" = ""fpc,fpc1020""
+ register "irq" = "IRQ_EDGE_LOW(GPP_C8_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 off end # SDCard
diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl
index 22b92f3..2882d50 100644
--- a/src/mainboard/google/eve/dsdt.asl
+++ b/src/mainboard/google/eve/dsdt.asl
@@ -67,7 +67,4 @@ DefinitionBlock(
{
#include "acpi/dptf.asl"
}
-
- /* ACPI code for EC functions */
- #include "acpi/mainboard.asl"
}
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