[coreboot-gerrit] New patch to review for coreboot: nb/intel/i945/raminit: Don't hardcode B2B read/write Command Spacing

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18355

-gerrit

commit d91548a3941704bd92e9bbc306724b77c781492b
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Mon Feb 13 01:12:02 2017 +0100

    nb/intel/i945/raminit: Don't hardcode B2B read/write Command Spacing
    
    This programs these timings according to "Mobile Intel® 945 Express
    Chipset Family Datasheet".
    
    UNTESTED!!
    
    Change-Id: I2888496c0467512411f57cbc5cfb75c50907b44f
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/i945/raminit.c | 58 +++++++++++++++++++++++++++++++-----
 1 file changed, 51 insertions(+), 7 deletions(-)

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 1f79cf6..93d46e8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1720,7 +1720,7 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo)
 
 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
 {
-	u32 reg32, tRD_min;
+	u32 reg32, tRD_min, ta;
 	u32 tWTR;
 	u32 temp_drt;
 	int i, page_size;
@@ -1774,9 +1774,6 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
 	reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
 	temp_drt |= (reg32 << 24);
 
-	/* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
-	temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
-
 	tRD_min = sysinfo->cas;
 	switch (sysinfo->fsb_frequency) {
 	case 533: break;
@@ -1787,6 +1784,56 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
 
 	temp_drt |= (tRD_min << 11);
 
+	ta = sysinfo->twr - tRD_min;
+
+	/* B2B Write-Read Command Spacing (Different Rank) */
+	reg32 = BURSTLENGTH / 2 + ta - 1;
+	switch (reg32) {
+	case 6:
+		temp_drt |= (0 << 22);
+		break;
+	case 5:
+	default:
+		temp_drt |= (1 << 22);
+		break;
+	case 4:
+		temp_drt |= (2 << 22);
+		break;
+	}
+
+	/* B2B Write-Read Command Spacing for BURSTLENGTH 8 */
+	reg32 = BURSTLENGTH / 2 + ta + 1;
+	switch (reg32) {
+	case 9:
+		temp_drt |= (0 << 20);
+		break;
+	case 8:
+		temp_drt |= (1 << 20);
+		break;
+	case 7:
+		temp_drt |= (2 << 20);
+		break;
+	case 6:
+	default:
+		temp_drt |= (3 << 20);
+		break;
+
+	}
+
+	/* B2B Write Command Spacing */
+	reg32 = BURSTLENGTH / 2 + ta;
+	switch (reg32) {
+	case 6:
+		temp_drt |= (0 << 18);
+		break;
+	case 5:
+		temp_drt |= (1 << 18);
+		break;
+	case 4:
+		temp_drt |= (2 << 18);
+		break;
+	}
+
 	/* Read Auto Precharge to Activate */
 
 	temp_drt |= (8 << 0);
@@ -1813,9 +1860,6 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
 	/* Pre-All to Activate Delay */
 	temp_drt |= (0 << 16);
 
-	/* Precharge to Precharge Delay stays at 1 clock */
-	temp_drt |= (0 << 18);
-
 	/* Activate to Precharge Delay */
 	temp_drt |= (sysinfo->tras << 19);