[coreboot-gerrit] Change in coreboot[master]: mainboard/google/zoombini: Add SoC acpi files to dsdt.asl

[Nick Vaccaro (Code Review)]

Hello Nick Vaccaro,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/23035

to review the following change.


Change subject: mainboard/google/zoombini: Add SoC acpi files to dsdt.asl
......................................................................

mainboard/google/zoombini: Add SoC acpi files to dsdt.asl

BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: I417a1c606e4968120414af57aa3b17d5c3b3cad0
Signed-off-by: Nick Vaccaro <nvaccaro at chromium.org>
---
M src/mainboard/google/zoombini/dsdt.asl
1 file changed, 11 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/23035/1

diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl
index b1faad6..c50a79a 100644
--- a/src/mainboard/google/zoombini/dsdt.asl
+++ b/src/mainboard/google/zoombini/dsdt.asl
@@ -24,14 +24,25 @@
 	0x20110725	// OEM revision
 )
 {
+	// Some generic macros
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+
 	// global NVS and variables
 	#include <soc/intel/cannonlake/acpi/globalnvs.asl>
 
 	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		}
 	}
 
 	#if IS_ENABLED(CONFIG_CHROMEOS)
 	// Chrome OS specific
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 	#endif
+
+	// Chipset specific sleep states
+	#include <soc/intel/cannonlake/acpi/sleepstates.asl>
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I417a1c606e4968120414af57aa3b17d5c3b3cad0
Gerrit-Change-Number: 23035
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro at chromium.org>
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