[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Program OPI PCR LPC registers

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22941


Change subject: soc/intel/cannonlake: Program OPI PCR LPC registers
......................................................................

soc/intel/cannonlake: Program OPI PCR LPC registers

According to PCH BIOS spec(570374) 2.4.1, DMI cycle decoding need to be
programmed before it got locked. Update lpc programming to add decode
programming in DMI side as well. Small core soc such as APL,GLK don't
have DMI interface, hence make the program optional with SOC.

BUG=b.70765863
TEST=Apply changes and add chromeos EC decoding in mainboard ec.c, read
back IO port in depthcharge cli and return is not zero.

Change-Id: I520afa8c5b2113efab7b224c7f3002fb30ff57f4
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/include/soc/pcr_ids.h
M src/soc/intel/common/block/lpc/lpc_lib.c
3 files changed, 36 insertions(+), 24 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/22941/1

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 0deece6..088c85e 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -28,30 +28,6 @@
 #include <soc/pm.h>
 #include <soc/smbus.h>
 
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1400
-#define PCR_PSFX_TO_SHDW_BAR0	0
-#define PCR_PSFX_TO_SHDW_BAR1	0x4
-#define PCR_PSFX_TO_SHDW_BAR2	0x8
-#define PCR_PSFX_TO_SHDW_BAR3	0xC
-#define PCR_PSFX_TO_SHDW_BAR4	0x10
-#define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
-#define PCR_PSFX_T0_SHDW_PCIEN	0x1C
-
-#define PCR_DMI_LPCLGIR1	0x2730
-#define PCR_DMI_LPCLGIR2	0x2734
-#define PCR_DMI_LPCLGIR3	0x2738
-#define PCR_DMI_LPCLGIR4	0x273c
-
-#define PCR_DMI_ACPIBA		0x27B4
-#define PCR_DMI_ACPIBDID	0x27B8
-#define PCR_DMI_PMBASEA		0x27AC
-#define PCR_DMI_PMBASEC		0x27B0
-#define PCR_DMI_TCOBASE		0x2778
-#define  TCOEN			(1 << 1)	/* Enable TCO I/O range decode. */
-
-#define PCR_DMI_LPCIOD		0x2770
-#define PCR_DMI_LPCIOE		0x2774
-
 static void enable_p2sbbar(void)
 {
 	device_t dev = PCH_DEV_P2SB;
diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
index 65576aa..9840f0b 100644
--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
@@ -35,4 +35,31 @@
 #define PID_LPC		0xc7
 #define PID_SERIALIO	0xcb
 
+/*
+ * OPI PCR register
+ */
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1400
+#define PCR_PSFX_TO_SHDW_BAR0	0
+#define PCR_PSFX_TO_SHDW_BAR1	0x4
+#define PCR_PSFX_TO_SHDW_BAR2	0x8
+#define PCR_PSFX_TO_SHDW_BAR3	0xC
+#define PCR_PSFX_TO_SHDW_BAR4	0x10
+#define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
+#define PCR_PSFX_T0_SHDW_PCIEN	0x1C
+
+#define PCR_DMI_LPCLGIR1	0x2730
+#define PCR_DMI_LPCLGIR2	0x2734
+#define PCR_DMI_LPCLGIR3	0x2738
+#define PCR_DMI_LPCLGIR4	0x273c
+
+#define PCR_DMI_ACPIBA		0x27B4
+#define PCR_DMI_ACPIBDID	0x27B8
+#define PCR_DMI_PMBASEA		0x27AC
+#define PCR_DMI_PMBASEC		0x27B0
+#define PCR_DMI_TCOBASE		0x2778
+/* Enable TCO I/O range decode. */
+#define  TCOEN			(1 << 1)
+
+#define PCR_DMI_LPCIOD		0x2770
+#define PCR_DMI_LPCIOE		0x2774
 #endif
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index b4b3d1b..6a0cda7 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -21,9 +21,13 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
 #include <lib.h>
 #include "lpc_def.h"
 #include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+
+#define PCR_LGIR_OFFSET (PCR_DMI_LPCLGIR1 - 0x84)
 
 void lpc_enable_fixed_io_ranges(uint16_t io_enables)
 {
@@ -32,6 +36,8 @@
 	reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
 	io_enables |= reg_io_enables;
 	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);
+	if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE))
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_enables);
 }
 
 /*
@@ -96,6 +102,9 @@
 		lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
 
 		pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
+		if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE))
+			pcr_write32(PID_DMI,
+				(lgir_reg_offset + PCR_LGIR_OFFSET), lgir);
 
 		printk(BIOS_DEBUG,
 		       "LPC: Opened IO window LGIR%d: base %llx size %x\n",

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I520afa8c5b2113efab7b224c7f3002fb30ff57f4
Gerrit-Change-Number: 22941
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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