<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22941">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Program OPI PCR LPC registers<br><br>According to PCH BIOS spec(570374) 2.4.1, DMI cycle decoding need to be<br>programmed before it got locked. Update lpc programming to add decode<br>programming in DMI side as well. Small core soc such as APL,GLK don't<br>have DMI interface, hence make the program optional with SOC.<br><br>BUG=b.70765863<br>TEST=Apply changes and add chromeos EC decoding in mainboard ec.c, read<br>back IO port in depthcharge cli and return is not zero.<br><br>Change-Id: I520afa8c5b2113efab7b224c7f3002fb30ff57f4<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/bootblock/pch.c<br>M src/soc/intel/cannonlake/include/soc/pcr_ids.h<br>M src/soc/intel/common/block/lpc/lpc_lib.c<br>3 files changed, 36 insertions(+), 24 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/22941/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>index 0deece6..088c85e 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>@@ -28,30 +28,6 @@</span><br><span> #include <soc/pm.h></span><br><span> #include <soc/smbus.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1400</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_TO_SHDW_BAR0 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_TO_SHDW_BAR1 0x4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_TO_SHDW_BAR2 0x8</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_TO_SHDW_BAR3 0xC</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_TO_SHDW_BAR4 0x10</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_T0_SHDW_PCIEN 0x1C</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_LPCLGIR1 0x2730</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_LPCLGIR2 0x2734</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_LPCLGIR3 0x2738</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_LPCLGIR4 0x273c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_ACPIBA 0x27B4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_ACPIBDID 0x27B8</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_PMBASEA 0x27AC</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_PMBASEC 0x27B0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_TCOBASE 0x2778</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_LPCIOD 0x2770</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_LPCIOE 0x2774</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void enable_p2sbbar(void)</span><br><span> {</span><br><span> device_t dev = PCH_DEV_P2SB;</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h</span><br><span>index 65576aa..9840f0b 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h</span><br><span>@@ -35,4 +35,31 @@</span><br><span> #define PID_LPC 0xc7</span><br><span> #define PID_SERIALIO 0xcb</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * OPI PCR register</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1400</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR1 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR2 0x8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR3 0xC</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_BAR4 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSFX_T0_SHDW_PCIEN 0x1C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_LPCLGIR1 0x2730</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_LPCLGIR2 0x2734</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_LPCLGIR3 0x2738</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_LPCLGIR4 0x273c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_ACPIBA 0x27B4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_ACPIBDID 0x27B8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_PMBASEA 0x27AC</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_PMBASEC 0x27B0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_TCOBASE 0x2778</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable TCO I/O range decode. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOEN (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_LPCIOD 0x2770</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_LPCIOE 0x2774</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>index b4b3d1b..6a0cda7 100644</span><br><span>--- a/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>+++ b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>@@ -21,9 +21,13 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/pci.h></span><br><span> #include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span> #include <lib.h></span><br><span> #include "lpc_def.h"</span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_LGIR_OFFSET (PCR_DMI_LPCLGIR1 - 0x84)</span><br><span> </span><br><span> void lpc_enable_fixed_io_ranges(uint16_t io_enables)</span><br><span> {</span><br><span>@@ -32,6 +36,8 @@</span><br><span> reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);</span><br><span> io_enables |= reg_io_enables;</span><br><span> pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE))</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_enables);</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>@@ -96,6 +102,9 @@</span><br><span> lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;</span><br><span> </span><br><span> pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE))</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI,</span><br><span style="color: hsl(120, 100%, 40%);">+ (lgir_reg_offset + PCR_LGIR_OFFSET), lgir);</span><br><span> </span><br><span> printk(BIOS_DEBUG,</span><br><span> "LPC: Opened IO window LGIR%d: base %llx size %x\n",</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22941">change 22941</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22941"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I520afa8c5b2113efab7b224c7f3002fb30ff57f4 </div>
<div style="display:none"> Gerrit-Change-Number: 22941 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>