[coreboot-gerrit] Change in coreboot[master]: drivers/mrc_cache: Make bootstate for SPI writes variable

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22937


Change subject: drivers/mrc_cache: Make bootstate for SPI writes variable
......................................................................

drivers/mrc_cache: Make bootstate for SPI writes variable

The default bootstate for writing MRC data to flash is BS_DEV_ENUMERATE
but this is too early for some implementations.  Add options to Kconfig
for allowing a different bootstate to be selected.

It is assumed SPI lockdown will always execute in the state immediately
following writing to flash.  The latest that may be allowed is
BS_OS_RESUME_CHECK, so the latest MRC data may be written is
BS_POST_DEVICE.  The earliest is maintained at BS_DEV_ENUMERATE.

Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/drivers/mrc_cache/Kconfig
M src/drivers/mrc_cache/mrc_cache.c
2 files changed, 35 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22937/1

diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig
index 3e0bdda..e15696d 100644
--- a/src/drivers/mrc_cache/Kconfig
+++ b/src/drivers/mrc_cache/Kconfig
@@ -28,4 +28,21 @@
 	bool
 	default n
 
+config MRC_WRITE_BOOTSTATE
+	int "Write MRC settings at bootstate"
+	range 2 6
+	default 2 # BS_DEV_ENUMERATE
+	help
+	  This option specifies when the MRC settings are written to NVRAM.
+	  The write occurs at the end of the bootstate indicated.  These
+	  definitions must be kept in sync with boot_state_t:
+	  2:  BS_DEV_ENUMERATE,
+	  3:  BS_DEV_RESOURCES,
+	  4:  BS_DEV_ENABLE,
+	  5:  BS_DEV_INIT,
+	  6:  BS_POST_DEVICE,
+
+	  Any NVRAM lockdown procedure will be run in the stage after writing
+	  the MRC settings, and before BS_OS_RESUME.
+
 endif # CACHE_MRC_SETTINGS
diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c
index 3a96896..c76f613 100644
--- a/src/drivers/mrc_cache/mrc_cache.c
+++ b/src/drivers/mrc_cache/mrc_cache.c
@@ -574,8 +574,23 @@
 }
 
 /*
- * Ensures MRC training data is stored into SPI after PCI enumeration is done
- * during BS_DEV_ENUMERATE-BS_ON_EXIT and lock down SPI protected ranges
- * during BS_DEV_RESOURCES-BS_ON_EXIT.
+ * Ensures MRC training data is stored into SPI after PCI enumeration is done.
+ * Some implementations may be require this to be later than others.  Locking
+ * down SPI protected ranges will occur at the end of the subsequent bootstate.
  */
+
+#if CONFIG_MRC_WRITE_BOOTSTATE == 8 /* BS_OS_RESUME */
+#error "Choose a different bootstate for writing MRC cache data"
+#endif
+
+#if CONFIG_MRC_WRITE_BOOTSTATE == 2
 BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL);
+#elif CONFIG_MRC_WRITE_BOOTSTATE == 3
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, update_mrc_cache, NULL);
+#elif CONFIG_MRC_WRITE_BOOTSTATE == 4
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, update_mrc_cache, NULL);
+#elif CONFIG_MRC_WRITE_BOOTSTATE == 5
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, update_mrc_cache, NULL);
+#elif CONFIG_MRC_WRITE_BOOTSTATE == 6
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, update_mrc_cache, NULL);
+#endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea
Gerrit-Change-Number: 22937
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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