[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Disable SATA controller

[Vaibhav Shankar (Code Review)]

Vaibhav Shankar has uploaded this change for review. ( https://review.coreboot.org/22875


Change subject: mainboard/intel/cannonlake_rvp: Disable SATA controller
......................................................................

mainboard/intel/cannonlake_rvp: Disable SATA controller

SATA was enabled only for internal testing. Since we do not use
SATA on chrome platforms, it can be disabled.

Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8
Signed-off-by: Vaibhav Shankar <vaibhav.shankar at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
2 files changed, 8 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/22875/1

diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 2f472e2..a874f4c 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -30,9 +30,9 @@
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
 	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
 
-	register "SataEnable" = "1"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
+	register "SataEnable" = "0"
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "0"
 
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaAudioLinkHda" = "1"
@@ -95,7 +95,7 @@
 		device pci 16.3 off end # Management Engine KT Redirection
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on  end # SATA
+		device pci 17.0 off  end # SATA
 		device pci 19.0 on  end # I2C #4
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index ca46d36..0d29a98 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -30,9 +30,9 @@
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
 	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
 
-	register "SataEnable" = "1"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
+	register "SataEnable" = "0"
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "0"
 
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaAudioLinkHda" = "1"
@@ -93,7 +93,7 @@
 		device pci 16.3 off end # Management Engine KT Redirection
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on  end # SATA
+		device pci 17.0 off  end # SATA
 		device pci 19.0 on  end # I2C #4
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8
Gerrit-Change-Number: 22875
Gerrit-PatchSet: 1
Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar at intel.com>
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