[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/bootblock/bootblock.c: Fix unused value
Richard Spiegel (Code Review)
gerrit at coreboot.org
Thu Dec 14 17:58:54 CET 2017
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22873
Change subject: soc/amd/stoneyridge/bootblock/bootblock.c: Fix unused value
......................................................................
soc/amd/stoneyridge/bootblock/bootblock.c: Fix unused value
In function load_smu_fw1(), variable base receives one value and is
immediately overwritten. Remove the first line, as it's useless.
This fixes CID 1383612
BUG=b:70620140
TEST=Build kahlee and boot.
Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/bootblock/bootblock.c
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/22873/1
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 030c990..f70b6d9 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -91,7 +91,6 @@
u32 base, limit;
/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
- base = 0x80000000;
base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
--
To view, visit https://review.coreboot.org/22873
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8
Gerrit-Change-Number: 22873
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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