[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add integrated LAN config parameters

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/22856


Change subject: soc/intel/skylake: Add integrated LAN config parameters
......................................................................

soc/intel/skylake: Add integrated LAN config parameters

Add parameters to configure the integrated LAN via FSP.  Since
this takes over a PCI CLKREQ# pin it needs to know which pin
it should use, and there are additional parameters for LTR and
a "K1 power save" feature.

This was tested on a KBL-R board with integrated LAN, verifying
that the device is functional under Linux with the e1000e driver.

Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
2 files changed, 10 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/22856/1

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index a7804af..8540e21 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -135,6 +135,10 @@
 
 	/* Lan */
 	u8 EnableLan;
+	u8 EnableLanLtr;
+	u8 EnableLanK1Off;
+	u8 LanClkReqSupported;
+	u8 LanClkReqNumber;
 
 	/* SATA related */
 	u8 EnableSata;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 2df013f..96c3b60 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -186,6 +186,12 @@
 	params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
 
 	params->PchLanEnable = config->EnableLan;
+	if (config->EnableLan) {
+		params->PchLanLtrEnable = config->EnableLanLtr;
+		params->PchLanK1OffEnable = config->EnableLanK1Off;
+		params->PchLanClkReqSupported = config->LanClkReqSupported;
+		params->PchLanClkReqNumber = config->LanClkReqNumber;
+	}
 	params->SataSalpSupport = config->SataSalpSupport;
 	params->SsicPortEnable = config->SsicPortEnable;
 	params->ScsEmmcEnabled = config->ScsEmmcEnabled;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Gerrit-Change-Number: 22856
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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