<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22856">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Add integrated LAN config parameters<br><br>Add parameters to configure the integrated LAN via FSP.  Since<br>this takes over a PCI CLKREQ# pin it needs to know which pin<br>it should use, and there are additional parameters for LTR and<br>a "K1 power save" feature.<br><br>This was tested on a KBL-R board with integrated LAN, verifying<br>that the device is functional under Linux with the e1000e driver.<br><br>Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>2 files changed, 10 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/22856/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h<br>index a7804af..8540e21 100644<br>--- a/src/soc/intel/skylake/chip.h<br>+++ b/src/soc/intel/skylake/chip.h<br>@@ -135,6 +135,10 @@<br> <br>     /* Lan */<br>     u8 EnableLan;<br>+        u8 EnableLanLtr;<br>+     u8 EnableLanK1Off;<br>+   u8 LanClkReqSupported;<br>+       u8 LanClkReqNumber;<br> <br>        /* SATA related */<br>    u8 EnableSata;<br>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c<br>index 2df013f..96c3b60 100644<br>--- a/src/soc/intel/skylake/chip_fsp20.c<br>+++ b/src/soc/intel/skylake/chip_fsp20.c<br>@@ -186,6 +186,12 @@<br>         params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;<br> <br>       params->PchLanEnable = config->EnableLan;<br>+      if (config->EnableLan) {<br>+          params->PchLanLtrEnable = config->EnableLanLtr;<br>+                params->PchLanK1OffEnable = config->EnableLanK1Off;<br>+            params->PchLanClkReqSupported = config->LanClkReqSupported;<br>+            params->PchLanClkReqNumber = config->LanClkReqNumber;<br>+  }<br>     params->SataSalpSupport = config->SataSalpSupport;<br>      params->SsicPortEnable = config->SsicPortEnable;<br>        params->ScsEmmcEnabled = config->ScsEmmcEnabled;<br></pre><p>To view, visit <a href="https://review.coreboot.org/22856">change 22856</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22856"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06 </div>
<div style="display:none"> Gerrit-Change-Number: 22856 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>