[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801ix: Use common ACPI PIRQ function
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sun Dec 10 15:13:49 CET 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22804
Change subject: sb/intel/i82801ix: Use common ACPI PIRQ function
......................................................................
sb/intel/i82801ix: Use common ACPI PIRQ function
This drops the 'mainboard specific' ACPI PIRQ code, since it is now
generated automatically.
Tested on X200: no IRQ related issues.
Change-Id: I5a01a0eb8de07d54c0dc326603f19c7eddab3886
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
D src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl
D src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
D src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl
M src/northbridge/intel/gm45/acpi/hostbridge.asl
M src/southbridge/intel/i82801ix/Kconfig
M src/southbridge/intel/i82801ix/lpc.c
6 files changed, 11 insertions(+), 243 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/22804/1
diff --git a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl
deleted file mode 100644
index aefdf94..0000000
--- a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * gm45
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Onboard GbE
- Package() { 0x0019ffff, 0, 0, 16 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, 0, 16 },
- Package() { 0x001affff, 1, 0, 17 },
- Package() { 0x001affff, 2, 0, 18 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 17 },
- Package() { 0x001dffff, 2, 0, 18 },
- // LPC bridge sub devices 0:1f.x
- Package() { 0x001fffff, 1, 0, 17 },
- Package() { 0x001fffff, 2, 0, 18 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard GbE
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // LPC bridge sub devices 0:1f.x
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
- })
- }
-}
diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
deleted file mode 100644
index aefdf94..0000000
--- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * gm45
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Onboard GbE
- Package() { 0x0019ffff, 0, 0, 16 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, 0, 16 },
- Package() { 0x001affff, 1, 0, 17 },
- Package() { 0x001affff, 2, 0, 18 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 17 },
- Package() { 0x001dffff, 2, 0, 18 },
- // LPC bridge sub devices 0:1f.x
- Package() { 0x001fffff, 1, 0, 17 },
- Package() { 0x001fffff, 2, 0, 18 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard GbE
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // LPC bridge sub devices 0:1f.x
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
- })
- }
-}
diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl
deleted file mode 100644
index 4a9ede8..0000000
--- a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * gm45
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, 0, 16 },
- Package() { 0x001affff, 1, 0, 17 },
- Package() { 0x001affff, 2, 0, 18 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 17 },
- Package() { 0x001dffff, 2, 0, 18 },
- // FIXME
- // CardBus/IEEE1394 0:1e.2, 0:1e.3
- // Package() { 0x001effff, 0, 0, 22 },
- // Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 16 },
- Package() { 0x001fffff, 1, 0, 17 },
- Package() { 0x001fffff, 2, 0, 18 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // FIXME
- // CardBus/IEEE1394 0:1e.2, 0:1e.3
- // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
- })
- }
-}
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl
index c674df5..afa7a61 100644
--- a/src/northbridge/intel/gm45/acpi/hostbridge.asl
+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl
@@ -228,6 +228,3 @@
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/gm45_pci_irqs.asl"
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 6879bce..24179b1 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -18,6 +18,7 @@
bool
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+ select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
select IOAPIC
select HAVE_USBDEBUG
select HAVE_HARD_RESET
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index bc45b9d..73b5fef 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -33,6 +33,7 @@
#include "i82801ix.h"
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
+#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <drivers/intel/gma/i915.h>
#define NMI_OFF 0
@@ -558,12 +559,21 @@
}
}
+/*
+ * Generates ACPI pirq routing on the assumption that reset
+ * defaults are used for DxxIR.
+ */
static void southbridge_fill_ssdt(device_t device)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
+
+ /*
+ * Generates PIRQ ACPI table with assumption DxxIR are at
+ * reset default. */
+ gen_def_acpi_pirq();
}
static struct pci_operations pci_ops = {
--
To view, visit https://review.coreboot.org/22804
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5a01a0eb8de07d54c0dc326603f19c7eddab3886
Gerrit-Change-Number: 22804
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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