<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22804">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801ix: Use common ACPI PIRQ function<br><br>This drops the 'mainboard specific' ACPI PIRQ code, since it is now<br>generated automatically.<br><br>Tested on X200: no IRQ related issues.<br><br>Change-Id: I5a01a0eb8de07d54c0dc326603f19c7eddab3886<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>D src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl<br>D src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl<br>D src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl<br>M src/northbridge/intel/gm45/acpi/hostbridge.asl<br>M src/southbridge/intel/i82801ix/Kconfig<br>M src/southbridge/intel/i82801ix/lpc.c<br>6 files changed, 11 insertions(+), 243 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/22804/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl<br>deleted file mode 100644<br>index aefdf94..0000000<br>--- a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl<br>+++ /dev/null<br>@@ -1,80 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* This is board specific information: IRQ routing for the<br>- * gm45<br>- */<br>-<br>-<br>-// PCI Interrupt Routing<br>-Method(_PRT)<br>-{<br>- If (PICM) {<br>- Return (Package() {<br>- // PCIe Graphics 0:1.0<br>- Package() { 0x0001ffff, 0, 0, 16 },<br>- // Onboard graphics (IGD) 0:2.0<br>- Package() { 0x0002ffff, 0, 0, 16 },<br>- // Onboard GbE<br>- Package() { 0x0019ffff, 0, 0, 16 },<br>- // USB and EHCI 0:1a.x<br>- Package() { 0x001affff, 0, 0, 16 },<br>- Package() { 0x001affff, 1, 0, 17 },<br>- Package() { 0x001affff, 2, 0, 18 },<br>- // High Definition Audio 0:1b.0<br>- Package() { 0x001bffff, 0, 0, 16 },<br>- // PCIe Root Ports 0:1c.x<br>- Package() { 0x001cffff, 0, 0, 16 },<br>- Package() { 0x001cffff, 1, 0, 17 },<br>- Package() { 0x001cffff, 2, 0, 18 },<br>- Package() { 0x001cffff, 3, 0, 19 },<br>- // USB and EHCI 0:1d.x<br>- Package() { 0x001dffff, 0, 0, 16 },<br>- Package() { 0x001dffff, 1, 0, 17 },<br>- Package() { 0x001dffff, 2, 0, 18 },<br>- // LPC bridge sub devices 0:1f.x<br>- Package() { 0x001fffff, 1, 0, 17 },<br>- Package() { 0x001fffff, 2, 0, 18 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- // PCIe Graphics 0:1.0<br>- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // Onboard graphics (IGD) 0:2.0<br>- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // Onboard GbE<br>- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // USB and EHCI 0:1a.x<br>- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- // High Definition Audio 0:1b.0<br>- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // PCIe Root Ports 0:1c.x<br>- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },<br>- // USB and EHCI 0:1d.x<br>- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- // LPC bridge sub devices 0:1f.x<br>- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }<br>- })<br>- }<br>-}<br>diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl<br>deleted file mode 100644<br>index aefdf94..0000000<br>--- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl<br>+++ /dev/null<br>@@ -1,80 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* This is board specific information: IRQ routing for the<br>- * gm45<br>- */<br>-<br>-<br>-// PCI Interrupt Routing<br>-Method(_PRT)<br>-{<br>- If (PICM) {<br>- Return (Package() {<br>- // PCIe Graphics 0:1.0<br>- Package() { 0x0001ffff, 0, 0, 16 },<br>- // Onboard graphics (IGD) 0:2.0<br>- Package() { 0x0002ffff, 0, 0, 16 },<br>- // Onboard GbE<br>- Package() { 0x0019ffff, 0, 0, 16 },<br>- // USB and EHCI 0:1a.x<br>- Package() { 0x001affff, 0, 0, 16 },<br>- Package() { 0x001affff, 1, 0, 17 },<br>- Package() { 0x001affff, 2, 0, 18 },<br>- // High Definition Audio 0:1b.0<br>- Package() { 0x001bffff, 0, 0, 16 },<br>- // PCIe Root Ports 0:1c.x<br>- Package() { 0x001cffff, 0, 0, 16 },<br>- Package() { 0x001cffff, 1, 0, 17 },<br>- Package() { 0x001cffff, 2, 0, 18 },<br>- Package() { 0x001cffff, 3, 0, 19 },<br>- // USB and EHCI 0:1d.x<br>- Package() { 0x001dffff, 0, 0, 16 },<br>- Package() { 0x001dffff, 1, 0, 17 },<br>- Package() { 0x001dffff, 2, 0, 18 },<br>- // LPC bridge sub devices 0:1f.x<br>- Package() { 0x001fffff, 1, 0, 17 },<br>- Package() { 0x001fffff, 2, 0, 18 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- // PCIe Graphics 0:1.0<br>- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // Onboard graphics (IGD) 0:2.0<br>- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // Onboard GbE<br>- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // USB and EHCI 0:1a.x<br>- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- // High Definition Audio 0:1b.0<br>- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // PCIe Root Ports 0:1c.x<br>- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },<br>- // USB and EHCI 0:1d.x<br>- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- // LPC bridge sub devices 0:1f.x<br>- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }<br>- })<br>- }<br>-}<br>diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl<br>deleted file mode 100644<br>index 4a9ede8..0000000<br>--- a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl<br>+++ /dev/null<br>@@ -1,80 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* This is board specific information: IRQ routing for the<br>- * gm45<br>- */<br>-<br>-<br>-// PCI Interrupt Routing<br>-Method(_PRT)<br>-{<br>- If (PICM) {<br>- Return (Package() {<br>- // PCIe Graphics 0:1.0<br>- Package() { 0x0001ffff, 0, 0, 16 },<br>- // Onboard graphics (IGD) 0:2.0<br>- Package() { 0x0002ffff, 0, 0, 16 },<br>- // USB and EHCI 0:1a.x<br>- Package() { 0x001affff, 0, 0, 16 },<br>- Package() { 0x001affff, 1, 0, 17 },<br>- Package() { 0x001affff, 2, 0, 18 },<br>- // High Definition Audio 0:1b.0<br>- Package() { 0x001bffff, 0, 0, 16 },<br>- // PCIe Root Ports 0:1c.x<br>- Package() { 0x001cffff, 0, 0, 16 },<br>- // USB and EHCI 0:1d.x<br>- Package() { 0x001dffff, 0, 0, 16 },<br>- Package() { 0x001dffff, 1, 0, 17 },<br>- Package() { 0x001dffff, 2, 0, 18 },<br>- // FIXME<br>- // CardBus/IEEE1394 0:1e.2, 0:1e.3<br>- // Package() { 0x001effff, 0, 0, 22 },<br>- // Package() { 0x001effff, 1, 0, 20 },<br>- // LPC device 0:1f.0<br>- Package() { 0x001fffff, 0, 0, 16 },<br>- Package() { 0x001fffff, 1, 0, 17 },<br>- Package() { 0x001fffff, 2, 0, 18 }<br>- })<br>- } Else {<br>- Return (Package() {<br>- // PCIe Graphics 0:1.0<br>- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // Onboard graphics (IGD) 0:2.0<br>- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // USB and EHCI 0:1a.x<br>- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- // High Definition Audio 0:1b.0<br>- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // PCIe Root Ports 0:1c.x<br>- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- // USB and EHCI 0:1d.x<br>- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>- // FIXME<br>- // CardBus/IEEE1394 0:1e.2, 0:1e.3<br>- // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },<br>- // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },<br>- // LPC device 0:1f.0<br>- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }<br>- })<br>- }<br>-}<br>diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl<br>index c674df5..afa7a61 100644<br>--- a/src/northbridge/intel/gm45/acpi/hostbridge.asl<br>+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl<br>@@ -228,6 +228,3 @@<br> <br> Return (MCRS)<br> }<br>-<br>-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */<br>-#include "acpi/gm45_pci_irqs.asl"<br>diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig<br>index 6879bce..24179b1 100644<br>--- a/src/southbridge/intel/i82801ix/Kconfig<br>+++ b/src/southbridge/intel/i82801ix/Kconfig<br>@@ -18,6 +18,7 @@<br> bool<br> select SOUTHBRIDGE_INTEL_COMMON<br> select SOUTHBRIDGE_INTEL_COMMON_SMBUS<br>+ select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN<br> select IOAPIC<br> select HAVE_USBDEBUG<br> select HAVE_HARD_RESET<br>diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c<br>index bc45b9d..73b5fef 100644<br>--- a/src/southbridge/intel/i82801ix/lpc.c<br>+++ b/src/southbridge/intel/i82801ix/lpc.c<br>@@ -33,6 +33,7 @@<br> #include "i82801ix.h"<br> #include "nvs.h"<br> #include <southbridge/intel/common/pciehp.h><br>+#include <southbridge/intel/common/acpi_pirq_gen.h><br> #include <drivers/intel/gma/i915.h><br> <br> #define NMI_OFF 0<br>@@ -558,12 +559,21 @@<br> }<br> }<br> <br>+/*<br>+ * Generates ACPI pirq routing on the assumption that reset<br>+ * defaults are used for DxxIR.<br>+ */<br> static void southbridge_fill_ssdt(device_t device)<br> {<br> device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));<br> config_t *chip = dev->chip_info;<br> <br> intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);<br>+<br>+ /*<br>+ * Generates PIRQ ACPI table with assumption DxxIR are at<br>+ * reset default. */<br>+ gen_def_acpi_pirq();<br> }<br> <br> static struct pci_operations pci_ops = {<br></pre><p>To view, visit <a href="https://review.coreboot.org/22804">change 22804</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22804"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5a01a0eb8de07d54c0dc326603f19c7eddab3886 </div>
<div style="display:none"> Gerrit-Change-Number: 22804 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>