[coreboot-gerrit] Change in coreboot[master]: commonlib: Add timestamp codes for AGESA

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22797


Change subject: commonlib: Add timestamp codes for AGESA
......................................................................

commonlib: Add timestamp codes for AGESA

BUG=b:70432544
TEST=Build & boot kahlee. Look at timestamps.

Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/commonlib/include/commonlib/timestamp_serialized.h
1 file changed, 32 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/22797/1

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 6c8d955..82ca064 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -77,6 +77,22 @@
 	TS_END_COPYVPD_RO = 551,
 	TS_END_COPYVPD_RW = 552,
 
+	/* 900-920 reserved for vendorcode extensions (900-920: AMD AGESA) */
+	TS_AGESA_INIT_RESET_START = 900,
+	TS_AGESA_INIT_RESET_DONE = 901,
+	TS_AGESA_INIT_EARLY_START = 902,
+	TS_AGESA_INIT_EARLY_DONE = 903,
+	TS_AGESA_INIT_POST_START = 904,
+	TS_AGESA_INIT_POST_DONE = 905,
+	TS_AGESA_INIT_ENV_START = 906,
+	TS_AGESA_INIT_ENV_DONE = 907,
+	TS_AGESA_INIT_MID_START = 908,
+	TS_AGESA_INIT_MID_DONE = 909,
+	TS_AGESA_INIT_LATE_START = 910,
+	TS_AGESA_INIT_LATE_DONE = 911,
+	TS_AGESA_INIT_RTB_START = 912,
+	TS_AGESA_INIT_RTB_DONE = 913,
+
 	/* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
 	TS_ME_INFORM_DRAM_WAIT = 940,
 	TS_ME_INFORM_DRAM_DONE = 941,
@@ -181,6 +197,22 @@
 	{ TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" },
 	{ TS_START_KERNEL,	"jumping to kernel" },
 
+	/* AMD AGESA related timestamps */
+	{ TS_AGESA_INIT_RESET_START,	"calling AmdInitReset" },
+	{ TS_AGESA_INIT_RESET_DONE,	"back from AmdInitReset" },
+	{ TS_AGESA_INIT_EARLY_START,	"calling AmdInitEarly" },
+	{ TS_AGESA_INIT_EARLY_DONE,	"back from AmdInitEarly" },
+	{ TS_AGESA_INIT_POST_START,	"calling AmdInitPost" },
+	{ TS_AGESA_INIT_POST_DONE,	"back from AmdInitPost" },
+	{ TS_AGESA_INIT_ENV_START,	"calling AmdInitEnv" },
+	{ TS_AGESA_INIT_ENV_DONE,	"back from AmdInitEnv" },
+	{ TS_AGESA_INIT_MID_START,	"calling AmdInitMid" },
+	{ TS_AGESA_INIT_MID_DONE,	"back from AmdInitMid" },
+	{ TS_AGESA_INIT_LATE_START,	"calling AmdInitLate" },
+	{ TS_AGESA_INIT_LATE_DONE,	"back from AmdInitLate" },
+	{ TS_AGESA_INIT_RTB_START,	"calling AmdInitRtb/AmdS3Save" },
+	{ TS_AGESA_INIT_RTB_DONE,	"back from AmdInitRtb/AmdS3Save" },
+
 	/* Intel ME related timestamps */
 	{ TS_ME_INFORM_DRAM_WAIT,	"waiting for ME acknowledgement of raminit"},
 	{ TS_ME_INFORM_DRAM_DONE,	"finished waiting for ME response"},

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6
Gerrit-Change-Number: 22797
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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