<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22797">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">commonlib: Add timestamp codes for AGESA<br><br>BUG=b:70432544<br>TEST=Build & boot kahlee. Look at timestamps.<br><br>Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/commonlib/include/commonlib/timestamp_serialized.h<br>1 file changed, 32 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/22797/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h<br>index 6c8d955..82ca064 100644<br>--- a/src/commonlib/include/commonlib/timestamp_serialized.h<br>+++ b/src/commonlib/include/commonlib/timestamp_serialized.h<br>@@ -77,6 +77,22 @@<br> TS_END_COPYVPD_RO = 551,<br> TS_END_COPYVPD_RW = 552,<br> <br>+ /* 900-920 reserved for vendorcode extensions (900-920: AMD AGESA) */<br>+ TS_AGESA_INIT_RESET_START = 900,<br>+ TS_AGESA_INIT_RESET_DONE = 901,<br>+ TS_AGESA_INIT_EARLY_START = 902,<br>+ TS_AGESA_INIT_EARLY_DONE = 903,<br>+ TS_AGESA_INIT_POST_START = 904,<br>+ TS_AGESA_INIT_POST_DONE = 905,<br>+ TS_AGESA_INIT_ENV_START = 906,<br>+ TS_AGESA_INIT_ENV_DONE = 907,<br>+ TS_AGESA_INIT_MID_START = 908,<br>+ TS_AGESA_INIT_MID_DONE = 909,<br>+ TS_AGESA_INIT_LATE_START = 910,<br>+ TS_AGESA_INIT_LATE_DONE = 911,<br>+ TS_AGESA_INIT_RTB_START = 912,<br>+ TS_AGESA_INIT_RTB_DONE = 913,<br>+<br> /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */<br> TS_ME_INFORM_DRAM_WAIT = 940,<br> TS_ME_INFORM_DRAM_DONE = 941,<br>@@ -181,6 +197,22 @@<br> { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" },<br> { TS_START_KERNEL, "jumping to kernel" },<br> <br>+ /* AMD AGESA related timestamps */<br>+ { TS_AGESA_INIT_RESET_START, "calling AmdInitReset" },<br>+ { TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" },<br>+ { TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" },<br>+ { TS_AGESA_INIT_EARLY_DONE, "back from AmdInitEarly" },<br>+ { TS_AGESA_INIT_POST_START, "calling AmdInitPost" },<br>+ { TS_AGESA_INIT_POST_DONE, "back from AmdInitPost" },<br>+ { TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" },<br>+ { TS_AGESA_INIT_ENV_DONE, "back from AmdInitEnv" },<br>+ { TS_AGESA_INIT_MID_START, "calling AmdInitMid" },<br>+ { TS_AGESA_INIT_MID_DONE, "back from AmdInitMid" },<br>+ { TS_AGESA_INIT_LATE_START, "calling AmdInitLate" },<br>+ { TS_AGESA_INIT_LATE_DONE, "back from AmdInitLate" },<br>+ { TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" },<br>+ { TS_AGESA_INIT_RTB_DONE, "back from AmdInitRtb/AmdS3Save" },<br>+<br> /* Intel ME related timestamps */<br> { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"},<br> { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"},<br></pre><p>To view, visit <a href="https://review.coreboot.org/22797">change 22797</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22797"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6 </div>
<div style="display:none"> Gerrit-Change-Number: 22797 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>