[coreboot-gerrit] Change in coreboot[master]: intel/sandybridge: Make timC training more robust.

[Tobias Diedrich (Code Review)]

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22776


Change subject: intel/sandybridge: Make timC training more robust.
......................................................................

intel/sandybridge: Make timC training more robust.

When using native raminit with https://review.coreboot.org/#/c/22683/
I've found that timC training usually fails unless the ram is
overspecced (i.e. DDR3L-1600 rated for 1.35V works most of the time with
native raminit as DDR3-1333 @1.5V).

Looking at the training data I've found that during timC training it is
reading register values in the 0-4000 range and checking for runs of 0,
but with the failing training the values don't go all the way down to 0.
The solution for me has been to do a thresholing pre-pass, after which
both the DDR3-1333 @1.5V and the DDR3L-1600 @1.35V work fine for me.

Tested:
- Intel NUC DCP847SKE
- RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V),
  boots fine with native raminit @1.5V
- RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V),
  boots fine with native raminit @1.35V
- Casual use with these settings

Untested:
- I haven't run any extensive longer memtest yet

Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71
Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 25 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22776/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index eaef5f7..955d44b 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1546,6 +1546,27 @@
 	wait_428c(channel);
 }
 
+static void threshold_preprocess(int *data, int count)
+{
+	int min = data[0];
+	int max = min;
+	int i;
+	for (i = 1; i < count; i++) {
+		if (min > data[i]) {
+			min = data[i];
+		}
+		if (max < data[i]) {
+			max = data[i];
+		}
+	}
+	int threshold = min/2 + max/2;
+	for (i = 0; i < count; i++) {
+		data[i] = data[i] > threshold;
+	}
+	printram("threshold=%d min=%d max=%d\n",
+		 threshold, min, max);
+}
+
 static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank)
 {
 	int timC;
@@ -1577,8 +1598,10 @@
 		}
 	}
 	FOR_ALL_LANES {
-		struct run rn =
-		    get_longest_zero_run(statistics[lane], MAX_TIMC + 1);
+		threshold_preprocess(
+			statistics[lane], ARRAY_SIZE(statistics[lane]));
+		struct run rn = get_longest_zero_run(
+			statistics[lane], ARRAY_SIZE(statistics[lane]));
 		ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle;
 		if (rn.all) {
 			printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n",

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71
Gerrit-Change-Number: 22776
Gerrit-PatchSet: 1
Gerrit-Owner: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
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