<p>Tobias Diedrich has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22776">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/sandybridge: Make timC training more robust.<br><br>When using native raminit with https://review.coreboot.org/#/c/22683/<br>I've found that timC training usually fails unless the ram is<br>overspecced (i.e. DDR3L-1600 rated for 1.35V works most of the time with<br>native raminit as DDR3-1333 @1.5V).<br><br>Looking at the training data I've found that during timC training it is<br>reading register values in the 0-4000 range and checking for runs of 0,<br>but with the failing training the values don't go all the way down to 0.<br>The solution for me has been to do a thresholing pre-pass, after which<br>both the DDR3-1333 @1.5V and the DDR3L-1600 @1.35V work fine for me.<br><br>Tested:<br>- Intel NUC DCP847SKE<br>- RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V),<br>  boots fine with native raminit @1.5V<br>- RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V),<br>  boots fine with native raminit @1.35V<br>- Casual use with these settings<br><br>Untested:<br>- I haven't run any extensive longer memtest yet<br><br>Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71<br>Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>---<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>1 file changed, 25 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22776/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c<br>index eaef5f7..955d44b 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.c<br>@@ -1546,6 +1546,27 @@<br>  wait_428c(channel);<br> }<br> <br>+static void threshold_preprocess(int *data, int count)<br>+{<br>+      int min = data[0];<br>+   int max = min;<br>+       int i;<br>+       for (i = 1; i < count; i++) {<br>+             if (min > data[i]) {<br>+                      min = data[i];<br>+               }<br>+            if (max < data[i]) {<br>+                      max = data[i];<br>+               }<br>+    }<br>+    int threshold = min/2 + max/2;<br>+       for (i = 0; i < count; i++) {<br>+             data[i] = data[i] > threshold;<br>+    }<br>+    printram("threshold=%d min=%d max=%d\n",<br>+            threshold, min, max);<br>+}<br>+<br> static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank)<br> {<br>  int timC;<br>@@ -1577,8 +1598,10 @@<br>             }<br>     }<br>     FOR_ALL_LANES {<br>-              struct run rn =<br>-                  get_longest_zero_run(statistics[lane], MAX_TIMC + 1);<br>+            threshold_preprocess(<br>+                        statistics[lane], ARRAY_SIZE(statistics[lane]));<br>+             struct run rn = get_longest_zero_run(<br>+                        statistics[lane], ARRAY_SIZE(statistics[lane]));<br>              ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle;<br>             if (rn.all) {<br>                         printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n",<br></pre><p>To view, visit <a href="https://review.coreboot.org/22776">change 22776</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22776"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 </div>
<div style="display:none"> Gerrit-Change-Number: 22776 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tobias Diedrich <ranma+coreboot@tdiedrich.de> </div>